📚 Computer Architecture Revision for IB and AQA | IB和AQA计算机体系结构考点精讲
Computer architecture forms the bedrock of all computing systems, describing how the central processing unit (CPU), memory, and input/output devices interact to execute instructions. For both IB (SL/HL) and AQA A-level Computer Science, a deep understanding of the Von Neumann model, the fetch-decode-execute cycle, and factors affecting processor performance is essential. This guide systematically collates every examinable concept, from the layout of registers and cache hierarchy to assembly language addressing modes and the principles of pipelining, ensuring you are fully equipped for multiple-choice questions, structured answers, and extended response essays.
计算机体系结构是所有计算系统的基石，它描述了中央处理器（CPU）、内存及输入/输出设备如何协同工作以执行指令。无论是IB文凭（标准/高级）还是AQA A-level计算机科学，深入理解冯·诺依曼模型、取指-译码-执行周期以及影响处理器性能的因素都至关重要。这份考点精讲系统性地整理了每一个可考概念——从寄存器与高速缓存层级结构，到汇编语言寻址模式与流水线原理，确保你完全能够应对选择题、结构化简答以及长文论述题。
1. The Von Neumann Architecture | 冯·诺依曼体系结构
The Von Neumann architecture is the foundation of nearly all modern computers. It stores both program instructions and data in a single, unified read-write memory. A key feature is the use of a single bus to transfer instructions and data, which can create the "Von Neumann bottleneck" since the processor may have to wait while one is being fetched. The architecture comprises a central processing unit that includes an arithmetic logic unit (ALU), a control unit (CU), and a variety of registers, all connected through a system bus to memory and I/O controllers.
冯·诺依曼体系结构是几乎所有现代计算机的基础。它将程序指令和数据都存放在同一个统一的读写存储器中。其关键特征是使用单一总线传输指令与数据，这会造成“冯·诺依曼瓶颈”，因为处理器可能需要等待另一项传输完成。此结构包含一个中央处理器，内含算术逻辑单元（ALU）、控制单元（CU）及各种寄存器，全部通过系统总线与内存和I/O控制器相连。
In contrast, the Harvard architecture uses separate storage and buses for instructions and data, allowing simultaneous access. While less common in general-purpose computers, it is found in digital signal processors and some microcontrollers. Both IB and AQA syllabi expect you to compare these architectures and explain why the Von Neumann model remains dominant despite its bottleneck.
与之相对，哈佛架构为指令和数据使用独立的存储空间和总线，允许同时访问。虽然它在通用计算机中不太常见，但广泛应用于数字信号处理器和某些微控制器。IB和AQA教学大纲均要求你比较这两种架构，并解释为何冯·诺依曼模型尽管存在瓶颈却依然占据主导地位。
2. CPU Components: ALU, CU & Registers | CPU组件：运算器、控制器与寄存器
The Arithmetic Logic Unit (ALU) performs all arithmetic operations (e.g. addition, subtraction) and logical operations (AND, OR, NOT, XOR). It receives operands from registers, processes them, and stores the result back into a register. The Control Unit (CU) directs the operation of the processor by sending control signals to other components. It decodes instructions fetched from memory, and coordinates the fetching of operands and the writing of results.
算术逻辑单元（ALU）执行所有算术运算（如加减法）和逻辑运算（与、或、非、异或）。它从寄存器获取操作数，处理后将结果存回寄存器。控制单元（CU）通过向其他部件发送控制信号来指挥处理器的工作。它对从内存取出的指令进行译码，并协调操作数的取出和结果的写回。
Registers are small, extremely fast storage locations within the CPU. The most important ones include: the Program Counter (PC), which holds the memory address of the next instruction to be fetched; the Memory Address Register (MAR), which holds the address of the memory location to be accessed; the Memory Data Register (MDR), also called Memory Buffer Register, which stores the data being transferred to or from memory; the Current Instruction Register (CIR), which holds the instruction currently being decoded and executed; and the Accumulator (ACC), which temporarily stores results produced by the ALU.
寄存器是CPU内部小巧且极快的小型存储位置。最重要的包括：程序计数器（PC），存储下一条待取指令的内存地址；内存地址寄存器（MAR），保存将要访问的内存单元地址；内存数据寄存器（MDR），也称内存缓冲寄存器，存储写入内存或从内存读出的数据；当前指令寄存器（CIR），保存当前正在译码执行的指令；累加器（ACC），临时存放ALU产生的结果。
3. The Fetch-Decode-Execute Cycle | 取指-译码-执行周期
This fundamental cycle describes how the CPU processes each instruction. In the fetch phase, the address held in the PC is copied into the MAR, and the CU sends a read signal to memory. The instruction stored at that address is transferred into the MDR and then copied into the CIR. At this point, the PC is incremented to point to the next instruction.
这一基本周期描述了CPU如何处理每一条指令。在取指阶段，PC中的地址被复制到MAR，同时CU向内存发出读信号。存放在该地址的指令被传送到MDR，随后复制到CIR。此时，PC自动递增以指向下一条指令。
During the decode stage, the CU interprets the bit pattern in the CIR to determine which operation to perform and which addressing mode or registers to use. In the execute stage, the CU sends necessary control signals to the ALU, registers, and data pathways to carry out the operation. For example, an addition instruction would cause the ALU to add two register values and place the sum into the accumulator. After execution, the cycle repeats from the fetch stage.
在译码阶段，CU解读CIR中的位模式，以确定执行何种操作以及使用哪种寻址模式或寄存器。在执行阶段，CU向ALU、寄存器及数据通路发送必要的控制信号以完成操作。例如，一条加法指令会让ALU将两个寄存器的值相加，并将和放入累加器。执行完毕后，周期从取指阶段重新开始。
4. Factors Affecting CPU Performance | 影响CPU性能的因素
Clock speed, measured in gigahertz (GHz), determines how many fetch-decode-execute cycles can occur per second. A faster clock means more instructions per unit time, but it also generates more heat. The number of cores enables true multitasking; a multi-core processor can handle multiple processes or threads simultaneously. However, the performance gain is not perfectly linear due to coordination overhead and software limitations. Cache memory, a small amount of high-speed static RAM located on or near the CPU, stores frequently accessed data and instructions, drastically reducing the average time to access memory.
时钟频率，以吉赫兹（GHz）为单位，决定了每秒能够发生多少次取指-译码-执行周期。时钟越快，单位时间内处理指令越多，但同时也会产生更多热量。处理器核心数量使得真正的多任务成为可能；多核处理器可以同时处理多个进程或线程。然而，由于协调开销和软件限制，性能提升并不完全呈线性。高速缓存是位于CPU内部或附近的小容量高速静态RAM，存储频繁访问的数据与指令，大幅降低了平均内存访问时间。
Word length, or the number of bits the CPU can process in one operation, also influences performance. A 64-bit processor can handle larger integers and address more memory than a 32-bit processor. In exam questions, you must often explain how each factor impacts performance and analyse trade-offs, such as the diminishing returns from adding more cores when a program is predominantly sequential.
字长，即CPU一次操作可处理的位数，同样影响性能。与32位处理器相比，64位处理器能处理更大的整数并寻址更多内存。在考试题目中，常常需要解释每种因素如何影响性能，并分析权衡关系，例如当程序以串行执行为主时，增加核心数量带来的性能提升会逐渐递减。
5. Primary Memory: RAM & ROM | 主存储器：RAM与ROM
Random Access Memory (RAM) is volatile memory used to store the operating system, application programs, and data currently in use. RAM can be read from and written to, but its contents are lost when power is turned off. Dynamic RAM (DRAM) uses capacitors and must be refreshed periodically, making it slower and cheaper, while Static RAM (SRAM) uses flip-flops, is faster and more expensive, and is typically found in cache.
随机存取存储器（RAM）是易失性存储器，用于存放正在使用的操作系统、应用程序及数据。RAM可读可写，但断电后内容丢失。动态RAM（DRAM）使用电容，需定期刷新，因此速度较慢且成本更低；而静态RAM（SRAM）采用触发器电路，速度更快、价格更贵，通常用于高速缓存。
Read-Only Memory (ROM) is non-volatile and typically holds the BIOS or firmware required to boot the computer. Data in ROM is retained even when the system is off. Modern systems often use flash memory for firmware updates. Understanding the differences between SRAM, DRAM, ROM, EPROM, and EEPROM is essential for both IB and AQA exams, especially when discussing memory hierarchy and boot sequences.
只读存储器（ROM）是非易失性的，通常存储启动计算机所需的BIOS或固件。即使在系统断电后，ROM中的数据依然保留。现代系统常使用闪存进行固件更新。理解SRAM、DRAM、ROM、EPROM和EEPROM之间的区别对IB和AQA考试至关重要，尤其是在讨论存储层次结构与引导序列时。
6. Cache Memory | 高速缓存
Cache memory sits between the CPU and main memory to bridge the speed gap. It operates on the principle of locality: temporal locality (recently accessed items are likely to be accessed again) and spatial locality (items near recently accessed locations are likely to be accessed). Caches are organised in levels: L1 cache is small, extremely fast, and integrated into the CPU core; L2 cache is larger but slower; L3 cache is even larger and shared among cores.
高速缓存位于CPU与主存之间，弥合速度差距。它基于局部性原理：时间局部性（近期访问过的项可能再次被访问）和空间局部性（临近近期访问位置的项很可能被访问）。缓存按层级组织：L1缓存容量小、速度极快，集成在处理器核心内部；L2缓存容量更大但速度稍慢；L3缓存容量更大且被各核心共享。
When the CPU needs data, it first checks L1 cache (cache hit). If the data is not there (cache miss), it checks L2, then L3, and finally main memory. A high cache hit rate significantly boosts performance. In exams, you may be asked to calculate performance improvements based on cache hit rates and access times, or to discuss how cache design impacts overall system efficiency.
当CPU需要数据时，首先检查L1缓存（缓存命中）。若数据不在那里（缓存未命中），则依次检查L2、L3，最后访问主存。高缓存命中率能显著提升性能。考试中可能会要求你根据缓存命中率与访问时间计算性能提升，或者讨论缓存设计如何影响整体系统效率。
7. Secondary Storage Technologies | 辅助存储技术
Secondary storage provides non-volatile, long-term data retention. Hard disk drives (HDDs) use spinning magnetic platters and read/write heads; they offer large capacities at low cost but have mechanical latency. Solid-state drives (SSDs) use NAND flash memory with no moving parts, giving faster read/write speeds and lower power consumption, but are generally more expensive per gigabyte. Optical discs (CD, DVD, Blu-ray) use lasers to read pits on a reflective surface.
辅助存储器提供非易失性的长期数据保存。硬盘驱动器（HDD）使用旋转的磁盘盘片和读写磁头；它们容量大、成本低，但存在机械延迟。固态驱动器（SSD）采用NAND闪存，无活动部件，读写速度更快，功耗更低，但每GB价格通常更高。光盘（CD、DVD、蓝光）利用激光读取反射面上的凹坑。
Both IB and AQA specifications expect you to compare these technologies in terms of speed, durability, portability, capacity, and cost. Additionally, cloud storage functions as a form of remote secondary storage, accessed via the internet, raising issues such as latency and security. Always be prepared to justify a choice of storage medium for a given scenario, such as using an SSD for a desktop OS boot drive and an HDD for a media server.
IB和AQA大纲均要求你从速度、耐用性、便携性、容量和成本方面比较这些技术。此外，云存储作为一种远程辅助存储形式，通过互联网访问，会引发延迟和安全等问题。要始终准备好为给定场景选择存储介质并进行辩护，例如台式机操作系统引导盘使用SSD，而媒体服务器使用HDD。
8. Instruction Set Architecture: CISC & RISC | 指令集架构：CISC与RISC
Complex Instruction Set Computer (CISC) architectures emphasise a large set of instructions, many of which can perform multi-step operations in a single instruction. Instructions vary in length and execution time. The goal is to reduce the number of instructions per program, simplifying compiler design. However, CISC chips tend to be more complex and power-hungry. Examples include the x86/x64 family used in most desktops and laptops.
复杂指令集计算机（CISC）架构强调拥有大量指令，其中许多指令可在单条指令中完成多步操作。指令长度和执行时间各异。其目标是减少每个程序的指令数，简化编译器设计。然而，CISC芯片往往更复杂且功耗更高。例如大多数台式机和笔记本电脑使用的x86/x64系列。
Reduced Instruction Set Computer (RISC) architectures utilise a small, highly optimised set of instructions, each typically executing in one clock cycle. Instructions are of fixed length, and a load-store architecture is used where only load and store instructions access memory. RISC processors are simpler, more energy-efficient, and allow fast pipelining. ARM processors, common in smartphones and embedded systems, are RISC-based. For exams, you must analyse the trade-offs and explain why RISC dominates mobile devices while CISC persists in servers and PCs.
精简指令集计算机（RISC）架构利用一组小而高度优化的指令，每条指令通常在一个时钟周期内完成执行。指令长度固定，并使用加载－存储架构，只有加载和存储指令可以访问内存。RISC处理器更简单、更节能，并能实现快速流水线。智能手机和嵌入式系统中常见的ARM处理器基于RISC。考试中，你必须分析权衡关系，并解释为何RISC主导移动设备，而CISC仍在服务器和PC中存续。
9. Assembly Language & Addressing Modes | 汇编语言与寻址模式
Assembly language provides a human-readable representation of machine code, using mnemonics like LDA, STA, ADD, SUB, JMP, and branching instructions. Each processor family has its own instruction set, and assembly code must be translated into machine code by an assembler. IB Computer Science Paper 2 and AQA structured questions often require you to trace or write simple assembly programs.
汇编语言提供了机器码的人类可读形式，使用诸如LDA、STA、ADD、SUB、JMP等助记符及分支指令。每个处理器家族都有自己的指令集，汇编代码必须由汇编器翻译为机器码。IB计算机科学试卷2和AQA结构化试题常常要求你跟踪或编写简单的汇编程序。
Addressing modes specify how the operand of an instruction is interpreted. Immediate addressing uses a literal value embedded in the instruction. Direct (absolute) addressing gives the memory address of the operand. Indirect addressing uses a register or memory location that holds the effective address of the operand. Indexed addressing adds a displacement to a base register to reach an array element. Understanding these modes is critical for determining the outcome of an instruction like LDA #5 versus LDA 5 versus LDA (R1).
寻址模式规定了如何解释指令中的操作数。立即寻址使用嵌入指令的字面值。直接（绝对）寻址给出操作数的内存地址。间接寻址使用一个寄存器或存储单元，其中保存操作数的有效地址。变址寻址将偏移量加到基址寄存器上以访问数组元素。理解这些模式对于区分诸如LDA #5、LDA 5和LDA (R1)的结果至关重要。
10. Buses & I/O Systems | 总线与输入/输出系统
A bus is a communication pathway that transfers data between components. The three main buses are: the data bus, which carries data bi-directionally; the address bus, which transmits memory addresses unidirectionally from the CPU to memory or I/O devices; and the control bus, which carries control signals like read, write, and interrupt requests. The width of the address bus determines the maximum addressable memory space (e.g., a 32-line bus can address up to 2³² locations).
总线是各部件间传输数据的通信通路。三种主要总线为：数据总线，双向传输数据；地址总线，单向将CPU的内存地址传送至内存或I/O设备；控制总线，携带读、写、中断请求等控制信号。地址总线的宽度决定了最大可寻址内存空间（例如，32条线的总线可寻址2³²个存储单元）。
Input/Output (I/O) can be managed through memory-mapped I/O, where I/O device registers appear as memory addresses, simplifying programming but reducing addressable RAM. Alternatively, isolated I/O uses dedicated I/O instructions and separate address spaces. Interrupts allow I/O devices to signal the CPU, avoiding the inefficiency of polling the device continuously. The interrupt handling process—saving the current state (PC, registers), executing the Interrupt Service Routine (ISR), and restoring the state—is a frequent exam topic.
输入/输出（I/O）可通过内存映射I/O管理，此时I/O设备寄存器表现为内存地址，简化了编程但减少了可寻址RAM空间。另一种方式是独立I/O，使用专用的I/O指令和独立的地址空间。中断允许I/O设备向CPU发出信号，避免了不断轮询设备的低效。中断处理过程——保存当前状态（PC、寄存器）、执行中断服务例程（ISR）、恢复状态——是常见的考试话题。
11. Pipelining (IB HL and AQA Extension) | 流水线技术（IB高级水平与AQA扩展）
Pipelining is a technique that overlaps the execution of multiple instructions by dividing the instruction cycle into stages. A classic RISC five-stage pipeline includes: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). While one instruction is being decoded, the next can be fetched, thus achieving an ideal throughput of one instruction per clock cycle after the pipeline is filled. This significantly improves performance without increasing clock frequency.
流水线是一种通过将指令周期划分为多个阶段来重叠执行多条指令的技术。经典的RISC五级流水线包括：取指（IF）、译码（ID）、执行（EX）、访存（MEM）、写回（WB）。当一条指令处于译码阶段时，下一条指令即可开始取指，从而在流水线充满后实现每时钟周期完成一条指令的理想吞吐率。这在无需提升时钟频率的情况下显著提升了性能。
Pipeline hazards can stall the pipeline. Data hazards arise when an instruction depends on the result of a prior instruction still in the pipeline; forwardings (or bypassing) can mitigate this. Control hazards occur due to branch instructions, which may cause the wrong instruction to be fetched. Techniques like branch prediction and delay slots are used. Both IB HL Paper 1 and AQA top-tier questions may require you to identify hazards in a given sequence and suggest solutions.
流水线冒险可能导致流水线停顿。数据冒险发生在一指令依赖前一条尚在流水线中的指令的结果时；可通过前推（旁路）技术缓解。控制冒险则源于分支指令，可能导致取入错误的指令。可使用分支预测和延迟槽等技术应对。IB高级水平试卷1和AQA高分题可能会要求你识别给定序列中的冒险并提出解决方案。
12. Boolean Logic and Basic Digital Circuits | 布尔逻辑与基本数字电路
The CPU's ALU and control logic are built from fundamental logic gates: AND, OR, NOT, NAND, NOR, XOR, and XNOR. These gates operate on binary inputs, and their behaviour is expressed in truth tables and Boolean algebra. Simple combinational circuits like half-adders and full-adders perform binary addition, while flip-flops form the basis of registers and memory elements used in sequential logic.
CPU的ALU与控制逻辑由基本逻辑门构成：与、或、非、与非、或非、异或、同或。这些门对二进制输入进行操作，其行为用真值表和布尔代数表达。简单组合逻辑电路如半加器和全加器执行二进制加法，而触发器构成了寄存器和顺序逻辑中存储器元件的基础。
For both IB and AQA courses, you must be able to analyse truth tables, simplify expressions using De Morgan's laws, and derive circuits from Boolean expressions. Additionally, understanding how a half-adder cascaded into a full-adder supports multi-bit binary addition directly links low-level electronics to the ALU operations you studied earlier. Expect questions that ask you to construct a full-adder circuit or evaluate a given logic gate network.
无论是IB还是AQA课程，你都必须能够分析真值表，运用德·摩根定理化简表达式，并根据布尔表达式推导电路。此外，理解半加器如何级联成全加器以支持多位二进制加法，直接关联到前期学习的ALU操作。预料会碰到要求你构建全加器电路或评估给定逻辑门网络的考题。
Published by TutorHao | Computer Science Revision Series | aleveler.com
更多咨询请联系16621398022（同微信）
或截图后用「扫一扫 → 相册」选择本图