📚 A-Level Edexcel Computer Science: Computer Architecture Key Points | A-Level Edexcel 计算机：计算机体系结构 考点精讲
Understanding computer architecture is fundamental to grasping how a computer functions, from the fetch-decode-execute cycle to the differences between CISC and RISC. This guide walks you through the essential concepts for the Edexcel A-Level Computer Science specification.
理解计算机体系结构是掌握计算机如何运作的基础，从取指-译码-执行周期到 CISC 与 RISC 的差异。本指南将带你梳理 Edexcel A-Level 计算机科学大纲中的核心概念。
1. Von Neumann Architecture | 冯·诺依曼架构
The Von Neumann architecture forms the basis of most modern computers. It features a single shared memory for both instructions and data, a central processing unit (CPU), and input/output mechanisms. The key idea is the stored-program concept, where instructions are stored in memory just like data.
冯·诺依曼架构构成了大多数现代计算机的基础。它的特点是使用单一共享存储器同时存放指令和数据，包含中央处理器（CPU）以及输入/输出机制。其核心思想是存储程序概念，即指令与数据一样存储在内存中。
This design uses a set of registers, a control unit (CU), and an arithmetic logic unit (ALU). Data and instructions must travel along the same bus, which can lead to the von Neumann bottleneck—a limitation where the speed of the processor is restricted by the transfer rate between memory and CPU.
该设计使用一组寄存器、控制单元（CU）和算术逻辑单元（ALU）。数据和指令必须通过同一条总线传输，这可能导致冯·诺依曼瓶颈——由于内存与 CPU 之间的传输率限制而制约处理器速度。
2. CPU Components | CPU 组件
The CPU consists of the Control Unit (CU), which decodes instructions and sends control signals to direct the operation of the processor; the Arithmetic Logic Unit (ALU), which performs arithmetic and logical operations; and a set of registers to store small amounts of data and status information.
CPU 由控制单元（CU）、算术逻辑单元（ALU）以及一组寄存器组成。控制单元负责译码指令并发送控制信号以指挥处理器操作；算术逻辑单元执行算术与逻辑运算；寄存器用于存储少量数据和状态信息。
The CU uses the clock signal to synchronize all activities. The ALU can handle operations like addition, subtraction, AND, OR, and NOT. Modern CPUs may have multiple ALUs to improve performance.
控制单元使用时钟信号同步所有活动。ALU 可处理加法、减法、与、或、非等操作。现代 CPU 可能拥有多个 ALU 以提升性能。
3. Special Purpose Registers | 专用寄存器
The processor has several dedicated registers that play crucial roles in the fetch-decode-execute cycle:
处理器拥有若干专用寄存器，在取指-译码-执行周期中起着关键作用：
- Program Counter (PC): holds the address of the next instruction to be fetched. / 程序计数器：存放下一条要取指的指令地址。
- Memory Address Register (MAR): holds the memory address from which data or an instruction will be read or written. / 内存地址寄存器：存放将要读取或写入数据/指令的内存地址。
- Memory Data Register (MDR): holds the actual data or instruction that has been read from memory or is to be written. / 内存数据寄存器：存放已从内存读取或将要写入的实际数据或指令。
- Current Instruction Register (CIR): stores the instruction currently being decoded and executed. / 当前指令寄存器：存储当前正在译码和执行的指令。
- Accumulator (ACC): temporarily stores results of ALU operations. / 累加器：临时存储 ALU 运算的结果。
These registers work together to manage the flow of data between the CPU and memory.
这些寄存器协同工作，管理 CPU 与内存之间的数据流。
4. System Buses | 系统总线
A bus is a set of parallel wires that transfer data between components. The three main buses are the address bus, data bus, and control bus.
总线是一组并行导线，用于在组件之间传输数据。主要的三类总线是地址总线、数据总线和控制总线。
- Address Bus: carries memory addresses from the processor to memory or I/O controllers. It is unidirectional. / 地址总线：将内存地址从处理器传输至内存或 I/O 控制器，是单向的。
- Data Bus: carries actual data between the processor, memory, and peripherals. It is bidirectional. / 数据总线：在处理器、内存和外围设备之间传输实际数据，是双向的。
- Control Bus: transmits control signals such as read, write, and interrupt requests. It is bidirectional. / 控制总线：传输控制信号，如读、写和中断请求，是双向的。
The width of the address bus determines the maximum addressable memory (e.g., 32-bit address bus can address 2³² memory locations). / 地址总线的宽度决定了可寻址内存的最大容量（例如，32 位地址总线可寻址 2³² 个内存单元）。
5. The Fetch-Decode-Execute Cycle | 取指-译码-执行周期
The CPU repeatedly carries out the fetch-decode-execute cycle to process instructions. The steps are:
CPU 反复执行取指-译码-执行周期来处理指令，步骤如下：
Fetch: The address in the PC is copied to the MAR; the PC is incremented. A read signal is sent, and the instruction is loaded from memory into the MDR, then transferred to the CIR.
取指：PC 中的地址被复制到 MAR；PC 递增。发送读信号，指令从内存加载到 MDR，然后传输至 CIR。
Decode: The CU decodes the instruction in the CIR and prepares the necessary control signals.
译码：CU 对 CIR 中的指令进行译码，并准备必要的控制信号。
Execute: The CPU performs the instruction, which may involve the ALU, memory access, or I/O. Results may be stored in the ACC or sent to memory.
执行：CPU 执行指令，可能涉及 ALU、内存访问或 I/O。结果可能存入 ACC 或发送至内存。
This cycle continues until the system is halted.
该循环持续进行，直至系统停机。
6. Factors Affecting CPU Performance | 影响 CPU 性能的因素
CPU performance is influenced by clock speed, number of cores, and cache memory.
CPU 性能受时钟速度、核心数和缓存的影响。
- Clock Speed: Measured in GHz, it determines how many cycles per second the CPU can execute. Higher clock speed generally means faster processing, but it also increases heat and power consumption. / 时钟速度：以 GHz 为单位，决定 CPU 每秒可执行多少个周期。更高的时钟速度通常意味着更快的处理速度，但也会增加热量和功耗。
- Number of Cores: A multi-core processor can handle multiple tasks or threads in parallel. Each core can operate independently, improving multitasking performance. However, not all software can fully utilize multiple cores. / 核心数：多核处理器可并行处理多个任务或线程。每个核心可独立运作，提高多任务性能。但并非所有软件都能充分利用多核。
- Cache Memory: A small, fast memory located on or near the CPU that stores frequently accessed data and instructions. Levels L1, L2, and L3 provide increasingly larger but slower storage. A larger cache reduces the need to access slower RAM, improving speed. / 缓存：位于 CPU 内部或附近的小型快速存储器，用于存放经常访问的数据和指令。L1、L2、L3 三级缓存提供容量递增但速度递减的存储。更大的缓存可减少对较慢 RAM 的访问，提升速度。
Other factors include instruction set architecture and bus width. / 其他因素包括指令集架构和总线宽度。
7. Pipelining | 流水线
Pipelining is a technique used to improve CPU throughput by overlapping the stages of the fetch-decode-execute cycle. While one instruction is being executed, the next can be decoded, and another fetched.
流水线是一种通过重叠取指-译码-执行周期的各阶段来提高 CPU 吞吐量的技术。当一条指令正在执行时，下一条可以进行译码，再下一条可以取指。
For example, in a 3-stage pipeline (Fetch, Decode, Execute), the processor can work on three instructions simultaneously at different stages. This increases instruction throughput but can introduce hazards such as data hazards (an instruction depends on a previous one) and branch hazards (pipeline flush when a branch is mispredicted).
例如，在三级流水线（取指、译码、执行）中，处理器可以同时处理三条处于不同阶段的指令。这提高了指令吞吐量，但可能引入数据冒险（某指令依赖于前一条指令的结果）和分支冒险（分支预测错误时需清空流水线）。
Modern processors use deeper pipelines and techniques like branch prediction and out-of-order execution to mitigate hazards.
现代处理器使用更深的流水线并采用分支预测、乱序执行等技术来缓解冒险。
8. Harvard Architecture | 哈佛架构
The Harvard architecture is an alternative to von Neumann that uses separate memory and buses for instructions and data. This allows the CPU to fetch an instruction and read/write data simultaneously, avoiding the von Neumann bottleneck.
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