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Computer Architecture for IB Computer Science: Key Points | IB 计算机：计算机体系结构 考点精讲

2026-07-15 01:08 · 本文部分内容由AI辅助创作

📚 Computer Architecture for IB Computer Science: Key Points | IB 计算机：计算机体系结构 考点精讲

Computer architecture is the design of the internal workings of a computer system: , including the CPU, the memory hierarchy, the buses and the input/output mechanisms that allow hardware and software to work together. In IB Computer Science you must be able to describe how an instruction is executed at at the hardware level, explain the role of of key components such as the Arithmetic Logic Unit (ALU), the control unit (CU) and the registers, and evaluate how caching, pipelining and multicore processors improve performance. This revision guide keeps every essential point and adds the formulas, comparisons and exam technique you need for full marks.

计算机体系结构是计算机系统内部工作原理的设计，包括 CPU、存储层次、总线和输入/输出机制，让软硬件能够协同工作。在 IB 计算机科学中，你需要描述指令在硬件层如何执行、解释算术逻辑单元 (ALU)、控制单元 (CU) 和寄存器等关键部件的作用，并评估缓存、流水线和多核处理器如何提升性能。本文保留全部核心考点，并补充公式、对比和答题技巧，帮助你拿到满分。

1. What Is Computer Architecture? | 什么是计算机体系结构

Computer architecture describes the structure and behaviour of the parts a programmer can see and control through instructions: the instruction set, the registers, the addressing modes and the way memory is organised. Computer organisation, by contrast, is the lower-level implementation - which gates, which circuit technology, which timings. IB questions usually ask about architecture, but strong answers mention both because a design decision at architecture level always has an implementation cost.

计算机体系结构描述程序员可以通过指令看到并控制的部分：指令集、寄存器、寻址方式以及内存的组织方式。而计算机组成则是更低层的实现——用哪些逻辑门、哪种电路工艺、什么样的时序。IB 的题目通常问的是体系结构，但优秀的答案会同时提到两者，因为体系结构层面的每个设计决策都对应着实现成本。

The three design goals are always in tension: speed, cost and power consumption. Every improvement in one usually harms at least one of the others, and this trade-off language is exactly what examiners want to see when a question says "discuss" or "evaluate".

三个设计目标始终相互牵制：速度、成本和功耗。任何一方面的改善通常都会损害至少另一方面，而 "discuss"（讨论）或 "evaluate"（评估）类题目要的正是这种权衡语言。

2. The Von Neumann Model and the Instruction Cycle | 冯·诺依曼模型与指令周期

The Von Neumann model stores both instructions and data in the same memory, connected to the CPU by a single set of buses. This "stored program" idea means a program can be loaded, modified and executed without rewiring the machine. Its weakness is the Von Neumann bottleneck: instructions and data compete for the same bus, so the CPU can starve while waiting for memory.

冯·诺依曼模型把指令和数据存放在同一块内存中，并通过同一组总线与 CPU 相连。这种 "存储程序" 思想意味着程序可以被载入、修改和执行，而无需改动硬件连线。它的弱点是冯·诺依曼瓶颈：指令和数据争用同一条总线，导致 CPU 在等待内存时处于饥饿状态。

Every instruction passes through the same repeated cycle:

每条指令都经历同一个循环：

3. Inside the CPU: ALU, Control Unit and Registers | CPU 内部：ALU、控制单元与寄存器

The CPU is the brain of the computer. Its primary components are the Arithmetic Logic Unit (ALU), which performs mathematical and logical operations, the Control Unit (CU), which directs the flow of data and decodes instructions, and a set of registers that provide ultra-fast storage for immediate data and addresses. All these parts communicate via internal buses.

CPU 是计算机的大脑。它主要由算术逻辑单元 (ALU)（执行算术与逻辑运算）、控制单元 (CU)（指挥数据流并译码指令）以及一组寄存器（为即时数据和地址提供超高速暂存）组成。这些部件通过内部总线相互通信。

The ALU can perform operations such as addition, subtraction, AND, OR, NOT and comparisons. It also sets condition flags - zero, negative, carry and overflow - and these flags are what make conditional branching possible. The CU fetches instructions from memory, interprets them, and sends control signals to other components, acting as the conductor of the whole machine. Registers like the Program Counter (PC) and Memory Address Register (MAR) play critical roles in this process.

ALU 可执行加、减、与、或、非、比较等运算。它还会设置条件标志位——零标志、负标志、进位标志和溢出标志，正是这些标志让条件跳转成为可能。CU 从内存取指令、翻译并发送控制信号给其他部件，相当于整台机器的指挥。程序计数器 (PC) 和内存地址寄存器 (MAR) 等寄存器在这个过程里起着关键作用。

Registers are the fastest storage in the system because they sit inside the CPU core and are addressed directly by the instruction, not by a memory address. Typical register roles worth memorising:

寄存器是系统中最快的存储，因为它们位于 CPU 内核内部，由指令直接指定而不是通过内存地址访问。值得记住的典型寄存器分工：

4. The Memory Hierarchy and Cache | 存储层次与缓存

Storage is arranged in a pyramid. At the top are registers, then cache (L1, L2, L3), then main memory (RAM), then secondary storage such as SSD and HDD, and finally offline or cloud backup. As you move down, capacity and cost per bit improve, but access time gets much longer. The hierarchy exists so that frequently used data sits close to the CPU while bulk data stays cheap.

存储按金字塔形排列。顶层是寄存器，然后是缓存（L1、L2、L3），再是主存 (RAM)，接着是 SSD、HDD 等二级存储，最后是离线或云端备份。越往下容量越大、单位成本越低，但访问时间显著变长。这一层次结构的意义在于：常用数据靠近 CPU，海量数据保持低价。

A cache is a small, fast block of memory between the CPU and RAM that holds recently or frequently used instructions and data. If the CPU finds what it needs in the cache it is a hit; if not, it is a miss and the block must be fetched from RAM, wasting many clock cycles.

缓存是位于 CPU 与 RAM 之间的一小块高速内存，保存最近或频繁使用的指令和数据。CPU 能在缓存中找到所需内容称为命中 (hit)；找不到称为未命中 (miss)，此时必须从 RAM 取回数据块，会浪费大量时钟周期。

Hit rate = cache hits ÷ total memory accesses

Caches work because of two principles of locality. Temporal locality means data used once is likely to be used again soon; spatial locality means data near an address just used is likely to be used next, which is why caches move whole blocks rather than single bytes. L1 is smallest and fastest and is per core; L2 is larger and slightly slower; L3 is shared between cores.

缓存之所以有效，靠的是两条局部性原理。时间局部性指刚用过的数据很可能很快再用；空间局部性指刚访问过的地址附近的数据很可能接下来被用到，这正是缓存按整块而非单个字节搬运的原因。L1 最小最快且每个核心独享；L2 更大、稍慢；L3 由各核心共享。

Write policy also matters. Write-through writes every change to both cache and RAM, which is simple and safe but slower. Write-back only writes to RAM when the block is evicted, which is faster but needs a dirty bit to track modified blocks.

写策略同样重要。写通 (write-through) 把每次修改同时写入缓存和 RAM，简单安全但较慢；写回 (write-back) 只在数据块被替换时才写回 RAM，速度更快，但需要脏位 (dirty bit) 来标记被修改过的块。

5. Buses and Data Transfer | 总线与数据传输

A bus is a set of parallel wires carrying signals between components. Three types are examined: the data bus carries the actual data and its width (8, 16, 32, 64 bits) sets how much can travel at once; the address bus carries the location being accessed and its width sets the maximum addressable memory; the control bus carries timing and command signals such as read, write, interrupt request and clock.

总线是一组在部件之间传输信号的并行导线。考试涉及三类：数据总线传输实际数据，其宽度（8、16、32、64 位）决定一次能传输多少；地址总线传输被访问的地址，其宽度决定最大可寻址内存；控制总线传输读、写、中断请求、时钟等时序与命令信号。

Maximum addressable memory = 2ⁿ locations, where n = address bus width

iB if each location holds one byte. A wider data bus increases throughput but needs more physical pins and traces, which raises cost - a classic trade-off answer.

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因此 32 位地址总线可寻址 2³² = 4 294 967 296 个位置，若每个位置存 1 字节，即 4 GiB。更宽的数据总线提高吞吐量，但需要更多引脚和走线，成本上升——这是典型的权衡式答案。

6. Input/Output, Polling, Interrupts and DMA | 输入/输出、轮询、中断与 DMA

Input/output devices are far slower than the CPU, so the CPU must not waste cycles waiting. Polling means the CPU repeatedly checks a device's status register; it is simple but wasteful because the CPU is busy doing nothing useful. Interrupts are better: the device sends a signal, the CPU finishes the current instruction, saves the contents of registers and the PC onto the stack, looks up the interrupt's priority and handler address in the interrupt vector table, runs the Interrupt Service Routine (ISR), then restores the saved state and continues.

输入/输出设备远比 CPU 慢，因此 CPU 不能把周期浪费在等待上。轮询 (polling) 指 CPU 反复检查设备的状态寄存器，简单但浪费，因为 CPU 忙于做无用功。中断更好：设备发出信号，CPU 完成当前指令，把寄存器和 PC 的内容保存到栈上，在中断向量表中查到中断优先级与处理程序地址，执行中断服务程序 (ISR)，之后恢复保存的状态继续运行。

Direct Memory Access (DMA) goes further: a DMA controller transfers blocks of data directly between a device and memory while the CPU continues working, raising an interrupt only when the whole transfer is complete. This is essential for disk reads, video streaming and network traffic. Buffers and spooling smooth out the speed mismatch between fast and slow devices.

直接内存访问 (DMA) 更进一步：DMA 控制器在设备与内存之间直接搬运数据块，CPU 同时继续工作，仅在整块传输完成时收到一次中断。这对磁盘读取、视频流和网络流量至关重要。缓冲区 (buffer) 与假脱机 (spooling) 则用来缓冲快慢设备之间的速度差异。

7. Pipelining | 流水线技术

Pipelining overlaps the stages of instruction execution so that several instructions are in progress at once. A classic five-stage pipeline is fetch, decode, execute, memory access and write back. While instruction 1 is executing, instruction 2 is being decoded and instruction 3 is being fetched, so throughput rises even though the latency of a single instruction does not change.

流水线把指令执行的各个阶段重叠起来，使多条指令同时处于处理中。经典的五级流水线是取指、译码、执行、访存和写回。当第 1 条指令执行时，第 2 条正在译码、第 3 条正在取指，因此即使单条指令的延迟不变，吞吐量也会提高。

Ideal speedup ≈ number of pipeline stages k

Pipelines are limited by hazards. Structural hazards occur when two instructions need the same hardware in the same cycle, for example memory for both a fetch and a data access. Data hazards occur when an instruction needs a result that has not yet been written back; forwarding and stalling are the usual fixes. Control hazards occur with branches, because the CPU does not yet know which instruction comes next; branch prediction, delayed branching and flushing are used to reduce the penalty.

流水线受冒险 (hazard) 限制。结构冒险指两条指令在同一周期争用同一硬件，例如取指和访存同时要内存。数据冒险指某条指令需要尚未写回的结果，常用解决方案是前递 (forwarding) 与停顿 (stalling)。控制冒险出现在分支处，因为 CPU 还不知道下一条指令在哪，可用分支预测、延迟分支和清空流水线来减少损失。

8. Multicore and Parallel Processing | 多核与并行处理

Clock speeds stopped rising around 2005 because of heat and power limits, so manufacturers put multiple processing cores on one chip instead. A multicore processor can run several threads truly simultaneously, which helps tasks that can be split into independent parts - video rendering, physics simulation, large matrix calculations - but gives little benefit to inherently sequential work.

由于发热和功耗限制，主频在 2005 年前后停止上升，厂商改而在单一芯片上放置多个处理核心。多核处理器可真正同时运行多个线程，对可拆分为独立部分的任务（视频渲染、物理仿真、大型矩阵计算）帮助很大，但对本质串行的工作几乎没有收益。

Speedup = 1 ÷ ((1 − P) + P ÷ N)

This is Amdahl's Law, where P is the fraction of the work that can be parallelised and N is the number of processors. It shows that even with infinite cores the sequential part sets a hard ceiling. Multicore systems also need cache coherency, because each core has its own L1 cache and could otherwise read stale data.

这就是阿姆达尔定律，其中 P 是可并行化的比例，N 是处理器数量。它说明即使核心无限多，串行部分仍设定了一个硬性上限。多核系统还需要缓存一致性 (cache coherency)，因为每个核心有自己的 L1 缓存，否则可能读到过期的数据。

9. Measuring Performance: Clock Speed, CPI and MIPS | 性能度量：主频、CPI 与 MIPS

Clock speed alone is a poor measure, because a processor with a lower clock rate but a better instruction set can finish a task sooner. The standard formula combines three factors:

单看主频是不好的度量，因为主频更低但指令集更优的处理器可能更早完成任务。标准公式把三个因素结合起来：

CPU time = Instruction count × CPI × Clock cycle time

, doubling the clock rate halves the execution time only if CPI and instruction count stay the same - which is rarely true. CPI stands for cycles per instruction and is an average across the whole program, weighted by how often each instruction type appears.

由于时钟周期 = 1 ÷ 主频，只有在 CPI 与指令数不变时，主频翻倍才会让执行时间减半——而现实中很少如此。CPI 指每条指令的平均时钟周期数，是按各类指令出现频率加权后对整个程序取的平均值。

MIPS = Clock rate ÷ (CPI × 10⁶)

MIPS means millions of instructions per second, and it is a convenient but flawed benchmark: it rewards machines that simply use many simple instructions, and it cannot be compared across different instruction sets. Benchmark suites with real workloads give a fairer picture.

MIPS 表示每秒百万条指令，方便但有缺陷：它奖励那些单纯使用大量简单指令的机器，且不能跨不同指令集比较。使用真实负载的基准测试套件才能给出更公平的评价。

10. RISC versus CISC | 精简指令集与复杂指令集

RISC (Reduced Instruction Set Computer) keeps instructions few, simple and fixed in length, so each usually completes in one cycle and pipelines beautifully. CISC (Complex Instruction Set Computer) offers many powerful instructions of variable length, so one instruction can do a great deal, but timing and pipelining become harder. Modern x86 chips are really hybrids: they decode CISC instructions into simpler micro-operations internally.

RISC（精简指令集计算机）的指令少、简单且长度固定，因此通常一个周期完成一条，非常适合流水线。CISC（复杂指令集计算机）提供大量长度可变、功能强大的指令，一条指令能做很多事，但时序和流水线设计更困难。现代 x86 芯片其实是混合体：它们在内部把 CISC 指令译码为更简单的微操作。

Feature RISC CISC
Instruction set size Small, simple, fixed length Large, complex, variable length
Addressing modes Few Many
Cycles per instruction Usually 1 Often several
Pipelining Easy and efficient Harder, needs micro-ops
Compiled code size Larger Smaller
Power consumption Lower Higher
Typical use Phones, tablets, ARM servers Desktops, laptops, x86 servers

11. Exam Question Types and Answering Technique | 高频题型与答题技巧

Command words decide the depth required. "State" needs one short point with no explanation; "describe" needs a clear account of what happens; "explain" needs a cause-and-effect chain; "compare" needs both similarities and differences in linked sentences; "evaluate" needs a judgement supported by trade-offs. Marks are awarded per correct idea, so short, precise sentences score better than long, vague paragraphs.

命令词决定答题深度。"State"（陈述）只需一个简短要点，无需解释；"describe"（描述）要清楚说明发生了什么；"explain"（解释）要有因果链条；"compare"（比较）要用相互呼应的句子写出相同点与不同点；"evaluate"（评估）要有基于权衡的判断。评分按正确要点给分，因此简短准确的句子比冗长含糊的段落更容易得分。

12. Quick Revision Checklist and Common Mistakes | 快速复习清单与常见错误

Use this list the night before the exam. If you can say each line out loud without notes, you are ready.

考前一夜用这份清单自测。如果每一行都能不看书说出口，你就准备好了。