Logic Gates in A-Level Computer Science | A-Level 计算机：逻辑门 考点精讲

📚 Logic Gates in A-Level Computer Science | A-Level 计算机：逻辑门 考点精讲

Logic gates are the fundamental building blocks of digital circuits. They perform basic logical functions on one or more binary inputs to produce a single binary output. Understanding their behaviour, truth tables, Boolean expressions, and how they combine to form complex circuits is essential for A-Level Computer Science. This revision guide covers all key concepts, from basic gates to Boolean algebra and logic simplification, ensuring you are fully prepared for exam-style questions.

逻辑门是数字电路的基本构建块。它们对一个或多个二进制输入执行基本的逻辑功能，产生一个二进制输出。理解它们的行为、真值表、布尔表达式以及它们如何组合形成复杂电路，对于A-Level计算机科学至关重要。本考点精讲涵盖从基本门到布尔代数和逻辑简化的所有关键概念，确保你为考试题型做好充分准备。

1. Binary Logic and Truth Values | 二进制逻辑与真值

In digital electronics, signals are represented using two voltage levels: high (usually denoted as 1 or TRUE) and low (0 or FALSE). This binary system underpins all logic gate operations. A truth table lists every possible combination of inputs and the corresponding output for a logic gate or circuit.

在数字电子学中，信号使用两个电压电平表示：高电平（通常表示为1或TRUE）和低电平（0或FALSE）。这个二进制系统是所有逻辑门操作的基础。真值表列出了逻辑门或电路的所有可能输入组合及其对应输出。

A truth table with n inputs has 2ⁿ rows. For example, a 2-input gate has 4 rows (00, 01, 10, 11).

具有n个输入的真值表有2ⁿ行。例如，一个2输入门有4行（00, 01, 10, 11）。

Positive logic uses +5V as 1 and 0V as 0, which is the convention adopted throughout A-Level specifications.

正逻辑使用+5V作为1，0V作为0，这是A-Level规范中采用的惯例。

2. Basic Logic Gates: AND, OR, NOT | 基本逻辑门：与门、或门、非门

The three fundamental gates are AND, OR, and NOT. The AND gate outputs 1 only if all its inputs are 1. The OR gate outputs 1 if at least one input is 1. The NOT gate (inverter) outputs the opposite of its single input.

三个基本门是与门、或门和非门。与门仅在所有输入均为1时输出1。或门只要至少有一个输入为1就输出1。非门（反相器）输出其单一输入的反值。

• AND Gate: Boolean expression: Q = A · B (or simply AB). Truth table: 00→0, 01→0, 10→0, 11→1.
• 与门：布尔表达式：Q = A · B（或简写为AB）。真值表：00→0, 01→0, 10→0, 11→1。
• OR Gate: Boolean expression: Q = A + B. Truth table: 00→0, 01→1, 10→1, 11→1.
• 或门：布尔表达式：Q = A + B。真值表：00→0, 01→1, 10→1, 11→1。
• NOT Gate: Boolean expression: Q = A̅ (or ¬A). Truth table: 0→1, 1→0.
• 非门：布尔表达式：Q = A̅（或¬A）。真值表：0→1, 1→0。

In circuit diagrams, AND is drawn with a D-shaped symbol, OR with a curved pointed shape, and NOT as a triangle with a small circle at the output.

在电路图中，与门画成D形符号，或门画成弧形尖头形状，非门画成一个三角形并在输出端有一个小圆圈。

3. Universal Gates: NAND and NOR | 通用门：与非门和或非门

NAND and NOR gates are called universal gates because any logic function can be implemented using only NAND gates or only NOR gates. This property is crucial in digital circuit design, allowing standardisation and cost reduction.

与非门和或非门被称为通用门，因为任何逻辑功能完全可以仅用与非门或仅用或非门实现。这一特性在数字电路设计中至关重要，允许标准化并降低成本。

A NAND gate is an AND gate followed by a NOT. Its Boolean expression is Q = (A · B)̅. Truth table: 00→1, 01→1, 10→1, 11→0.

与非门是一个与门后接一个非门。其布尔表达式为Q = (A · B)̅。真值表：00→1, 01→1, 10→1, 11→0。

A NOR gate is an OR gate followed by a NOT. Boolean expression: Q = (A + B)̅. Truth table: 00→1, 01→0, 10→0, 11→0.

或非门是一个或门后接一个非门。布尔表达式：Q = (A + B)̅。真值表：00→1, 01→0, 10→0, 11→0。

4. Exclusive Gates: XOR and XNOR | 异或门和同或门

The XOR (exclusive OR) gate outputs 1 only when an odd number of inputs are 1. For two inputs, it gives 1 when inputs are different. The XNOR (exclusive NOR) gate outputs 1 when both inputs are the same, i.e., it is the complement of XOR.

异或门（XOR）仅在输入中1的个数为奇数时输出1。对于两个输入，当输入不同时输出1。同或门（XNOR）在两个输入相同时输出1，即它是XOR的补。

XOR Gate: Q = A ⊕ B = A·B̅ + A̅·B. Truth table: 00→0, 01→1, 10→1, 11→0.

异或门：Q = A ⊕ B = A·B̅ + A̅·B。真值表：00→0, 01→1, 10→1, 11→0。

XNOR Gate: Q = A ⊙ B = (A ⊕ B)̅ = A·B + A̅·B̅. Truth table: 00→1, 01→0, 10→0, 11→1.

同或门：Q = A ⊙ B = (A ⊕ B)̅ = A·B + A̅·B̅。真值表：00→1, 01→0, 10→0, 11→1。

XOR is widely used in arithmetic circuits (e.g., half adders) and parity checking. XNOR serves as an equality detector.

XOR广泛用于算术电路（如半加器）和奇偶校验。XNOR用作相等检测器。

5. Truth Tables and Boolean Expressions | 真值表与布尔表达式

Every logic circuit can be described by a truth table and a Boolean expression. Writing the Boolean expression from a truth table is typically done using the sum-of-products (SOP) method: identify rows where output is 1, form product terms (AND) of all inputs (inverting if the input is 0), then sum (OR) all these products.

每个逻辑电路都可以用真值表和布尔表达式描述。根据真值表编写布尔表达式通常使用乘积之和（SOP）方法：找出输出为1的行，构成所有输入（若输入为0则取反）的乘积项（AND），然后将所有这些乘积相加（OR）。

ample: For a function F with truth table rows 01→1 and 10→1 (inputs A, B), SOP gives F = A̅·B + A·B̅, which simplifies to A ⊕ B.

示例：对于函数F，真值表行为01→1和10→1（输入A、B），SOP得到F = A̅·B + A·B̅，可简化为A ⊕ B。

Product-of-sums (POS) is an alternative method, taking rows where output is 0, forming sum terms, and then ANDing them, but SOP is more common at A-Level.

和之积（POS）是另一种方法，取输出为0的行形成和项，然后相与，但在A-Level中SOP更为常见。

6. Combining Logic Gates into Circuits | 组合逻辑门构建电路

Real-world digital systems are built by connecting multiple logic gates. You must be able to analyse a given circuit diagram to produce its truth table and Boolean expression, and conversely, design a circuit from a specification.

现实世界的数字系统是由多个逻辑门连接而成的。你必须能够分析给定的电路图以生成其真值表和布尔表达式，反之，根据规格设计电路。

When analysing a circuit, label intermediate outputs, write their expressions step by step, and combine them. Always follow the precedence: NOT > AND > OR unless parentheses override.

分析电路时，标记中间输出，逐步写出它们的表达式，然后组合。始终遵循优先级：非 > 与 > 或，除非括号覆盖。

uces Q = (AB)·(B+C). Evaluating this over all 8 input combinations yields the truth table.

例如，一个电路输入A、B、C，第一个与门给出AB，第二个或门给出B+C，然后最终的与门产生Q = (AB)·(B+C)。评估所有8个输入组合即可得出真值表。

7. Boolean Algebra Laws and Simplification | 布尔代数定律与化简

Boolean algebra provides rules to simplify logic expressions, reducing the number of gates required. Key laws include:

布尔代数提供了简化逻辑表达式的规则，减少所需门数量。关键定律包括：

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• Identity: A + 0 = A, A · 1 = A
• 零/壹律：A + 0 = A, A · 1 = A
• Annihilation: A + 1 = 1, A · 0 = 0
• 吸收律：A + 1 = 1, A · 0 = 0
• Idempotent: A + A = A, A · A = A
• 幂等律：A + A = A, A · A = A
• Complement: A + A̅ = 1, A · A̅ = 0
• 互补律：A + A̅ = 1, A · A̅ = 0
• Double Negation: (A̅)̅ = A
• 双重否定律：(A̅)̅ = A
• Commutative: A + B = B + A, A · B = B · A
• 交换律：A + B = B + A, A · B = B · A
• Associative: (A + B) + C = A + (B + C), same for AND
• 结合律：(A + B) + C = A + (B + C)，与运算同理
• Distributive: A · (B + C) = A·B + A·C, A + (B·C) = (A+B)·(A+C)
• 分配律：A · (B + C) = A·B + A·C, A + (B·C) = (A+B)·(A+C)
• Absorption: A + (A·B) = A, A · (A + B) = A
• 吸收律：A + (A·B) = A, A · (A + B) = A
• De Morgan's Laws: (A·B)̅ = A̅ + B̅, (A+B)̅ = A̅ · B̅
• 德摩根定律：(A·B)̅ = A̅ + B̅, (A+B)̅ = A̅ · B̅

Using these laws, you can reduce complex expressions step by step. Always show your working in exams.

利用这些定律，你可以逐步简化复杂表达式。考试中务必展示解题步骤。

8. De Morgan's Theorem and Gate Equivalence | 德摩根定理与门等价

De Morgan's theorem is extremely useful for converting AND/OR logic to NAND/NOR and for simplifying circuits with inverted inputs. The two forms are:

德摩根定理对于将与或逻辑转换为与非/或非以及简化带反相输入的电路非常有用。两种形式为：

(A · B)̅ = A̅ + B̅

(A + B)̅ = A̅ · B̅

This demonstrates that a NAND gate can be represented as an OR gate with both inputs inverted. Similarly, a NOR gate is equivalent to an AND gate with inverted inputs. These transformations become essential when implementing circuits using only NAND or NOR gates.

这表明一个与非门可以表示为带两个反相输入的或门。类似地，或非门相当于带反相输入的与门。当仅使用与非门或或非门实现电路时，这些转换变得至关重要。

Exam tip: When asked to implement a given function solely with NAND gates, apply De Morgan's law to convert any OR operation into a NAND with inverted inputs, then cascade properly.

考试提示：当要求仅用与非门实现给定函数时，应用德摩根定律将任何或运算转换为带反相输入的与非门，然后适当地级联。

9. Combinational Logic Design & Half/Full Adders | 组合逻辑设计与半加器/全加器

Combinational circuits are those whose outputs depend only on the current inputs. Two key examples are the half adder and full adder, fundamental in binary addition.

组合电路是指输出仅取决于当前输入的电路。两个关键示例是半加器和全加器，它们是二进制加法的基础。

A half adder adds two single bits, A and B, producing sum (S) and carry (C). S = A ⊕ B, C = A · B. It consists of one XOR and one AND gate.

一个半加器将两个单比特A和B相加，产生和（S）和进位（C）。S = A ⊕ B，C = A · B。它由一个异或门和一个与门组成。

A full adder adds three bits: A, B, and an incoming carry Cᵢₙ. Outputs: S = A ⊕ B ⊕ Cᵢₙ, Cₒᵤₜ = A·B + Cᵢₙ·(A ⊕ from two half adders and an OR gate. Full adders are cascaded to create multi-bit adders.

一个全加器将三个比特相加：A、B和进位输入Cᵢₙ。输出：S = A ⊕ B ⊕ Cᵢₙ，Cₒᵤₜ = A·B + Cᵢₙ·(A ⊕ B)。它可以由两个半加器和一个或门构成。全加器级联可构成多位加法器。

Understanding these helps you see how logic gates are applied in arithmetic logic units (ALUs).

理解这些有助于你了解逻辑门如何在算术逻辑单元（ALU）中应用。

10. Logic Simplification Using Karnaugh Maps | 使用卡诺图进行逻辑简化

Karnaugh maps (K-maps) provide a graphical method to simplify Boolean expressions with up to four variables. A K-map arranges truth table terms in a grid so that adjacent cells differ by only one variable, enabling visual grouping of 1s to form simplified product terms.

卡诺图（K-map）提供了一种图形化方法，用于简化最多四个变量的布尔表达式。卡诺图将真值表项排列在网格中，使得相邻单元格仅相差一个变量，从而可以可视化地将1分组形成简化的乘积项。

For a 2-variable K-map (A,B), cells represent A̅B̅, A̅B, AB̅, AB. Groups of 1,2, or 4 form terms where the constant variables are kept and complemented variables are dropped. For example, grouping two adjacent 1s covering A̅B and AB gives B (since A varies).

对于2变量卡诺图（A,B），单元格表示A̅B̅, A̅B, AB̅, AB。1、2或4的分组形成保持恒定变量、去除补变量的项。例如，将两个相邻的1分组覆盖A̅B和AB，得到B（因为A变化）。

For 3 and 4 variables, the map follows Gray code order (00, 01, 11, 10) to ensure adjacency. You must be able to draw a K-map from a truth table or expression, group 1s in largest possible groups (powers of 2), and derive the minimal SOP expression.

对于3和4变量，图遵循格雷码顺序（00, 01, 11, 10）以确保相邻性。你必须能够根据真值表或表达式绘制卡诺图，以尽可能大的组（2的幂次）对1进行分组，并导出最简SOP表达式。

K-maps are especially helpful for identifying hazards and simplifying functions with don't-care conditions (marked as X).

卡诺图对于识别险象和简化带有无关条件（标记为X）的函数特别有帮助。

11. Logic Gate Implementation in Hardware | 逻辑门的硬件实现

At the hardware level, logic gates are built using transistors. In CMOS technology, both N-channel and P-channel MOSFETs are used. A NAND gate in CMOS typically uses two PMOS transistors in parallel and two NMOS in series. NOR gate has the opposite arrangement. This complementary structure ensures low static power consumption.

在硬件层面，逻辑门使用晶体管构建。在CMOS技术中，同时使用N沟道和P沟道MOSFET。CMOS与非门通常使用两个并联的PMOS管和两个串联的NMOS管。或非门结构相反。这种互补结构确保了较低的静态功耗。

Gate propagation delay is the time taken for a change at the input to be reflected at the output. This limits the speed of digital circuits. Fan-out refers to the number of standard loads a gate output can drive. These concepts appear in A-Level computer science when discussing processor architecture limitations.

门传播延迟是指输入变化反映到输出所需的时间。这限制了数字电路的速度。扇出是指一个门输出能驱动的标准负载数量。这些概念在A-Level计算机科学讨论处理器架构限制时会出现。

12. Common Pitfalls and Exam Tips | 常见误区与考试技巧

Many students mistakenly draw truth tables with inputs in the wrong order or forget that a NOT gate changes the logical value. Always list input combinations in ascending binary order: 00, 01, 10, 11 for two bits.

许多学生错误地以错误顺序绘制真值表，或忘记非门会改变逻辑值。始终按递增二进制顺序列出输入组合：对于两位，00, 01, 10, 11。

When simplifying Boolean expressions, show each step and state the law applied. If a K-map is used, clearly mark the groupings and convert them correctly to a minimal expression.

简化布尔表达式时，展示每一步并说明应用的定律。如果使用卡诺图，清楚地标记分组并正确转换为最简表达式。

Don't confuse XOR with inclusive OR; XOR is true only when inputs differ. For NAND/NOR universal gate questions, practice converting common functions (e.g., NOT, AND, OR) using only the specified gate type.

不要将异或与普通或混淆；异或仅在输入不同时为真。对于与非/或非通用门问题，练习只使用指定门类型转换常见函数（如非、与、或）。

In circuit design problems, always verify by testing a few input combinations mentally against the given specification.

在电路设计问题中，始终通过在脑海中对给定规格测试几个输入组合来验证。

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