📚 A-Level CIE Computer Science: CPU Revision Guide | A-Level CIE 计算机：CPU 考点精讲
The central processing unit (CPU) is the brain of the computer, responsible for executing instructions and processing data. For CIE A-Level Computer Science, a thorough understanding of the CPU's architecture, its components, the fetch-decode-execute cycle, and factors affecting performance is essential. This article consolidates the key concepts, explains them in detail, and highlights common examination points.
中央处理器（CPU）是计算机的大脑，负责执行指令和处理数据。对于 CIE A-Level 计算机科学来说，深入理解 CPU 的体系结构、组成部件、取指-解码-执行周期以及影响性能的因素至关重要。本文梳理了核心概念，逐一详细讲解，并指出常见考点。
1. Overview of CPU and Von Neumann Architecture | CPU 与冯·诺依曼架构概述
The CPU operates on the stored program concept, where both instructions and data are stored in the same memory. This is the foundation of the Von Neumann architecture. It consists of a control unit (CU), an arithmetic logic unit (ALU), registers, and buses that connect these components.
CPU 基于存储程序概念工作，即指令和数据存放在同一个存储器中。这是冯·诺依曼架构的基础。该架构由控制器（CU）、算术逻辑单元（ALU）、寄存器以及连接这些部件的总线组成。
In the Von Neumann model, instructions are fetched from memory one at a time, decoded, and then executed. This sequential processing is the core of the fetch-decode-execute cycle.
在冯·诺依曼模型中，指令每次从内存中取出一条，解码然后执行。这种顺序处理是取指-解码-执行周期的核心。
A key feature of this architecture is the use of a single shared memory for both data and instructions, which can lead to the 'Von Neumann bottleneck' where the bus becomes a limiting factor.
该架构的一个重要特征是使用单一共享存储器存放数据和指令，这可能导致“冯·诺依曼瓶颈”——总线成为限制性能的因素。
2. Components of the CPU | CPU 的组成部分
The CPU's internal structure includes three main functional units: the Control Unit (CU), the Arithmetic Logic Unit (ALU), and a set of registers. Each plays a distinct role in instruction processing.
CPU 的内部结构包含三个主要功能单元：控制器（CU）、算术逻辑单元（ALU）和一组寄存器。每个单元在指令处理中扮演不同的角色。
The Control Unit directs the operation of the processor. It decodes instructions, generates control signals to coordinate data movement, and manages the flow of information between the CPU and other components.
控制器指挥处理器的运行。它解码指令，生成控制信号以协调数据移动，并管理 CPU 与其他部件之间的信息流动。
The ALU performs arithmetic operations (addition, subtraction) and logical operations (AND, OR, NOT, XOR). It also handles comparisons and shift operations. The ALU receives operands from registers, processes them, and stores the result back into a register.
ALU 执行算术运算（加法、减法）和逻辑运算（AND、OR、NOT、XOR）。它还负责比较和移位操作。ALU 从寄存器接收操作数，处理后把结果存回寄存器。
Registers are small, high-speed storage locations inside the CPU. They hold data, instructions, and addresses temporarily during execution. Key registers are discussed in Section 4.
寄存器是 CPU 内部的小型高速存储位置。它们在执行期间临时保存数据、指令和地址。关键寄存器将在第 4 节讨论。
3. The System Bus | 系统总线
The system bus is a set of parallel wires that connect the CPU to memory and input/output devices. It is divided into three distinct buses: the address bus, the data bus, and the control bus.
系统总线是一组并行导线，将 CPU 连接到存储器和输入/输出设备。它分为三个独立的总线：地址总线、数据总线和控制总线。
The address bus carries memory addresses from the CPU to memory or I/O controllers. It is unidirectional (from CPU outwards). The width of the address bus determines the maximum addressable memory space. For example, a 32-line address bus can address 2³² memory locations.
地址总线从 CPU 向存储器或 I/O 控制器传送内存地址。它是单向的（从 CPU 向外）。地址总线的宽度决定了最大可寻址内存空间。例如，32 位地址总线可以寻址 2³² 个存储位置。
The data bus carries the actual data being transferred. It is bidirectional, allowing data to flow between CPU, memory, and peripherals. The width of the data bus affects how many bits can be transferred in one go; a wider data bus increases data throughput.
数据总线传送实际的数据。它是双向的，允许数据在 CPU、存储器和外设之间流动。数据总线的宽度影响一次能传输多少位；更宽的数据总线能提高数据吞吐量。
The control bus carries control signals such as read, write, clock, interrupt, and bus request/grant signals. It is a collection of individual lines, some from the CPU (output) and some to the CPU (input).
控制总线传送控制信号，如读、写、时钟、中断和总线请求/允许信号。它是一组独立的线路，有些由 CPU 发出（输出），有些进入 CPU（输入）。
4. Key Registers and Their Roles | 关键寄存器及其作用
Registers are vital for the fetch-decode-execute cycle. Each register has a dedicated purpose. In CIE specifications, you need to know the Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Current Instruction Register (CIR), Accumulator (ACC), and Index Register (IX).
寄存器对取指-解码-执行周期至关重要。每个寄存器有专用用途。在 CIE 大纲中，你需要掌握程序计数器（PC）、内存地址寄存器（MAR）、内存数据寄存器（MDR）、当前指令寄存器（CIR）、累加器（ACC）和变址寄存器（IX）。
Program Counter (PC): Holds the address of the next instruction to be fetched. It is automatically incremented after each fetch, unless a jump instruction alters its value.
程序计数器（PC）： 保存下一条要取出的指令的地址。每次取指后自动递增，除非遇到跳转指令改变它的值。
Memory Address Register (MAR): Holds the address of the memory location to be read from or written to. It receives the address from the PC during instruction fetch, or from a register during data access.
内存地址寄存器（MAR）： 保存要读或写的内存位置的地址。取指令时它从 PC 获取地址，访问数据时从其他寄存器获取地址。
Memory Data Register (MDR): Contains the data that has been read from memory or is about to be written to memory. Also known as the Memory Buffer Register (MBR).
内存数据寄存器（MDR）： 存放刚从内存读出的数据，或者即将写入内存的数据。也称为内存缓冲寄存器（MBR）。
Current Instruction Register (CIR): Stores the instruction that has just been fetched from memory. The CU then decodes the opcode and operand fields stored in the CIR.
当前指令寄存器（CIR）： 存储刚刚从内存取出的指令。然后 CU 解码 CIR 中的操作码和操作数字段。
Accumulator (ACC): A general-purpose register that temporarily holds results of ALU operations. Many arithmetic and logic instructions use the accumulator as an implicit operand.
累加器（ACC）： 一个通用寄存器，临时保存 ALU 运算的结果。许多算术和逻辑指令将累加器作为隐含操作数。
Index Register (IX): Used for indexed addressing; its value is added to an operand to form an effective address. This facilitates access to array elements or data structures.
变址寄存器（IX）： 用于变址寻址；其值加上操作数得到有效地址。这便于访问数组元素或数据结构。
5. The Fetch-Decode-Execute Cycle | 取指-解码-执行周期
This is the fundamental operational process of the CPU. Each cycle processes one instruction. The steps are repeated continuously while the computer is running. The cycle can be divided into three stages:
这是 CPU 的基本运行过程。每个周期处理一条指令。计算机运行时，这三个阶段不断重复。周期分为三个步骤：
Fetch: The address in PC is copied to MAR. The CU sends a read signal on the control bus. The memory unit places the instruction from that address onto the data bus, which is then copied into the MDR. The instruction is then transferred to the CIR. Finally, the PC is incremented to point to the next instruction.
取指： PC 中的地址复制到 MAR。CU 在控制总线上发送读信号。内存单元将该地址处的指令放到数据总线上，然后被复制到 MDR。指令随后传送到 CIR。最后 PC 递增，指向下一条指令地址。
Decode: The instruction in the CIR is split into opcode and operand(s). The CU interprets the opcode and generates the necessary control signals for the execute stage. If an operand refers to a memory address, that address may be calculated and placed in MAR.
解码： CIR 中的指令被分割为操作码和操作数。CU 解释操作码，并生成执行阶段所需的控制信号。如果操作数引用内存地址，该地址可以被计算并放入 MAR。
Execute: The ALU performs the required operation (e.g., arithmetic, logic, data transfer). If data is needed from memory, the address in MAR is used, data is read into MDR, and then moved to a register. The result is stored in a register (often the ACC) or written back to memory.
执行： ALU 执行所需的运算（如算术、逻辑、数据传送）。如果需要从内存取数据，则使用 MAR 中的地址，数据读入 MDR，然后移入寄存器。结果存入寄存器（通常是 ACC）或写回内存。
Examination tip: you should be able to describe these steps using the register transfers, e.g., MAR ← [PC], MDR ← [Memory], CIR ← [MDR], PC ← [PC] + 1.
考试提示：你应该能用寄存器传送语言描述这些步骤，如 MAR ← [PC]、MDR ← [Memory]、CIR ← [MDR]、PC ← [PC] + 1。
6. Factors Affecting CPU Performance | 影响 CPU 性能的因素
CIE exam questions frequently ask you to explain how clock speed, number of cores, and cache memory influence performance. A balanced answer includes the effect and an example or limitation.
CIE 考题经常要求解释时钟速度、核心数量和高速缓存如何影响性能。完整的答案应包含影响效果以及一个示例或局限性。
Clock Speed: Measured in Hertz (Hz); it determines how many fetch-decode-execute cycles can occur per second. A higher clock speed means more instructions per second, but it also increases heat and power consumption. Beyond a certain point, memory access times may cause the processor to wait (the memory wall).
时钟速度： 以赫兹（Hz）为单位；它决定了每秒可以发生多少次取指-解码-执行周期。更高的时钟速度意味着每秒更多指令，但也会增加热量和功耗。超过一定限度后，内存访问时间可能导致处理器等待（内存墙）。
Number of Cores: A multi-core CPU contains multiple independent processing units. This allows parallel execution of tasks. However, the performance gain depends on software being written to take advantage of multiple cores. Amdahl’s law states that the speedup is limited by the serial portion of the program.
核心数量： 多核 CPU 包含多个独立的处理单元，允许并行执行任务。但性能提升取决于软件是否针对多核进行编写。阿姆达尔定律指出，加速比受限于程序中的串行部分。
Cache Memory: Cache is a small amount of very fast memory located close to or on the CPU. It stores frequently used instructions and data, reducing the time needed to access main memory. Levels L1 (fastest, smallest), L2, and L3 (larger, slower) exist. The hit rate describes the proportion of accesses satisfied from cache. Larger cache generally improves performance, but at increased cost.
高速缓存： 缓存是位于 CPU 内部或附近的小容量极快速内存。它存储常用指令和数据，减少访问主存所需的时间。缓存分为 L1（最快、最小）、L2 和 L3（更大、较慢）等层级。命中率描述了从缓存成功访问的比例。更大的缓存通常提升性能，但成本更高。
7. Instruction Set and Opcode/Operand | 指令集与操作码/操作数
An instruction is a binary pattern that tells the CPU what operation to perform. It typically consists of two parts: the opcode (operation code) and the operand(s). The opcode specifies the operation (e.g., ADD, SUB, LOAD, STORE), while the operand represents the data or the address of the data.
指令是一个二进制模式，告诉 CPU 执行什么操作。它通常包含两部分：操作码（opcode）和操作数。操作码指定操作类型（如 ADD、SUB、LOAD、STORE），操作数代表数据或数据的地址。
The instruction format may vary: zero-address (operand implied, e.g., RET), one-address (one operand, ACC implied), two-address (source and destination), or three-address. CIE uses simplified assembly language with one or two operands.
指令格式可以不同：零地址（操作数隐含，如 RET）、一地址（一个操作数，ACC 隐含）、二地址（源和目的）或三地址。CIE 使用简化汇编语言，通常为一个或两个操作数。
For example, in the instruction ADD R1, 5, the opcode might be 1010 and the operand field encodes register R1 and the immediate value 5. Understanding the bit allocation helps to appreciate how the CU decodes instructions.
例如，指令 ADD R1, 5 中，操作码可能为 1010，操作数字段编码了寄存器 R1 和立即数 5。理解位分配有助于领悟 CU 如何解码指令。
8. Addressing Modes | 寻址模式
Addressing modes define how the operand of an instruction is interpreted to find the actual data (the effective address). CIE requires knowledge of immediate, direct, indirect, and indexed addressing.
寻址模式定义了如何解释指令的操作数以找到实际数据（有效地址）。CIE 需要掌握立即寻址、直接寻址、间接寻址和变址寻址。
Immediate addressing: The operand itself is the data. No memory access is needed for the data. Useful for constants. Example: LOAD #5 loads the literal value 5 into the accumulator.
立即寻址： 操作数本身就是数据。无需访问内存获取数据，常用于常量。示例：LOAD #5 将字面值 5 装入累加器。
Direct addressing: The operand gives the memory address of the data. The CPU accesses that memory location to get the data. Example: LOAD 500 loads the contents of memory location 500.
直接寻址： 操作数给出数据所在的内存地址。CPU 访问该内存位置以获取数据。示例：LOAD 500 装入内存地址 500 的内容。
Indirect addressing: The operand specifies an address that contains another address, which then contains the data. It requires two memory accesses. This is shown by brackets: LOAD (500) means look at address 500 to find an address, then load data from that second address.
间接寻址： 操作数指定一个地址，该地址中存放着另一个地址，后者才是数据的最终位置。需要两次内存访问。用括号表示：LOAD (500) 意为查看地址 500 以找到一个地址，再从该地址加载数据。
Indexed addressing: The operand is added to the contents of the index register to form the effective address. This is ideal for stepping through arrays. Example: LOAD 1000, X where X is the index register; effective address = 1000 + [X].
变址寻址： 将操作数与变址寄存器的内容相加，形成有效地址。非常适用于遍历数组。示例：LOAD 1000, X，其中 X 是变址寄存器；有效地址 = 1000 + [X]。
9. Interrupts and Their Handling | 中断及其处理
An interrupt is a signal from a hardware device or software that causes the CPU to temporarily suspend its current task, save its state, and execute a special routine called an Interrupt Service Routine (ISR). After handling the interrupt, the CPU resumes the original task.
中断是来自硬件设备或软件的信号，它导致 CPU 暂时挂起当前任务，保存其状态，并执行一个称为中断服务程序（ISR）的特殊例程。处理完中断后，CPU 恢复原来的任务。
The typical sequence for handling an interrupt: when an interrupt occurs, the CPU finishes executing the current instruction. The contents of PC and other essential registers are saved onto the stack. The PC is loaded with the start address of the ISR (from an interrupt vector table). The ISR executes. On completion, the saved registers are restored, and execution resumes from the interrupted instruction.
典型的中断处理流程：当中断发生时，CPU 完成当前指令的执行。PC 和其他关键寄存器的内容被保存到栈中。PC 被加载为 ISR 的起始地址（来自中断向量表）。ISR 执行。完成后，恢复保存的寄存器，从被中断的指令处继续执行。
Interrupts improve system responsiveness and efficiency because the CPU does not need to continuously poll devices. They are used for I/O operations, timers, error conditions, and software exceptions.
中断提高了系统的响应性和效率，因为 CPU 不需要持续轮询设备。它们用于 I/O 操作、定时器、错误条件和软件异常。
10. Pipelining | 流水线技术
Pipelining is a technique used to improve CPU throughput by overlapping the stages of multiple instructions. While one instruction is being executed, the next is being decoded, and the one after that is being fetched. This parallelises the fetch-decode-execute cycle.
流水线是一种通过重叠多条指令的不同阶段来提高 CPU 吞吐量的技术。当一条指令正在执行时，下一条正在解码，再下一条正在取指。这使取指-解码-执行周期并行化。
A simple three-stage pipeline (fetch, decode, execute) or a more realistic five-stage pipeline is common. The theoretical speedup is equal to the number of stages, but in practice, pipeline hazards reduce efficiency.
简单的三级流水线（取指、解码、执行）或更实际的五级流水线很常见。理论加速比等于流水线级数，但实际上流水线冲突（冒险）降低了效率。
Pipeline hazards: Data hazards occur when an instruction depends on the result of a previous instruction that is not yet complete. Control hazards arise from branch instructions where the next instruction to fetch is not known until the branch is resolved. Structural hazards happen when hardware resources are insufficient. Techniques like forwarding, stalling, and branch prediction are used to mitigate these.
流水线冒险： 数据冒险发生在某指令依赖于前一条指令的结果，而该结果尚未完成时。控制冒险源于分支指令，在下一条要取的指令在分支被解析之前未知。结构冒险发生在硬件资源不足时。采用前递、暂停和分支预测等技术来缓解这些冒险。
11. CISC vs RISC Architectures | CISC 与 RISC 架构对比
CIE expects you to compare Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC) designs. The distinction lies in the instruction set philosophy and hardware complexity.
CIE 要求你比较复杂指令集计算机（CISC）和精简指令集计算机（RISC）设计。区别在于指令集哲学和硬件复杂度。
| Feature | CISC | RISC |
|---|---|---|
| Instruction set | Large, complex instructions, many addressing modes | Small, simple, fixed-length instructions |
| Execution | Microcode / multi-cycle | Hardwired, single-cycle per instruction (ideally) |
| Pipelining | Difficult due to variable instruction length and timing | Easier, as instructions are uniform |
| Register set | Fewer registers, often specialised | Many general-purpose registers |
| Memory access | Instructions can operate directly on memory | Only LOAD/STORE instructions access memory |
| Compiler complexity | Simpler compiler; complex microcode | More work for compiler; simpler hardware |
Modern processors often blend RISC and CISC features, but the classic comparison remains a common examination topic.
现代处理器常常混合 RISC 和 CISC 特点，但经典对比仍是常见考题。
12. Summary of Key Points | 关键考点总结
To excel in the CPU topic, ensure you can: (1) label a CPU diagram and explain the role of each component; (2) describe the fetch-decode-execute cycle using register-level pseudocode; (3) explain how clock speed, cores, and cache affect performance and their limitations; (4) distinguish between different addressing modes with examples; (5) outline the interrupt handling process; (6) define pipelining and identify types of hazards; and (7) compare CISC and RISC architectures. Practice past paper questions to reinforce these concepts.
要在 CPU 专题中取得高分，请确保你能做到：(1) 标注 CPU 框图并解释各部件的功能；(2) 用寄存器级伪代码描述取指-解码-执行周期；(3) 解释时钟速度、核心数量和缓存如何影响性能及其局限性；(4) 举例区分不同寻址模式；(5) 概述中断处理过程；(6) 定义流水线并识别冒险类型；(7) 对比 CISC 与 RISC 架构。通过练习历年真题来巩固这些概念。
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