📚 Tricky Questions Explained: IB & OCR Computer Science | IB OCR 计算机易错题精讲
Welcome to our focused revision guide on the most common tricky questions that trip up students in IB and OCR Computer Science. From binary overflow to finite state machines, we will break down typical mistakes, explain the correct reasoning, and reinforce the underlying theory. Each section pairs a real exam-style pitfall with a step-by-step walkthrough, helping you avoid losing marks on subtle concepts.
欢迎阅读我们的易错题精讲指南，专门针对 IB 和 OCR 计算机科学课程中学生最易出错的问题。从二进制溢出、浮点规格化，到有限状态机，我们将逐一剖析常见错误，讲解正确思路，巩固关键概念。每个小节都以真实考题中的陷阱为引，逐步分析，帮你避开那些容易丢分的细节。
1. Two's Complement Overflow Detection | 二进制补码溢出检测
Consider adding two 8-bit two’s complement numbers: 01101010₂ (106₁₀) and 01011001₂ (89₁₀). Many students perform the binary addition and obtain 11000011₂, then incorrectly claim there is no overflow because the result fits in 8 bits. However, in two’s complement representation, the most significant bit (MSB) is the sign bit. Two positive numbers added together must produce a positive result; an MSB of 1 indicates a negative value, so overflow has occurred. The true decimal sum 195 exceeds the maximum 8-bit signed integer (+127), confirming the overflow. The rule: when adding operands with the same sign, if the result has a different sign, overflow is present.
考虑两个 8 位二进制补码数相加：01101010₂ (106₁₀) 和 01011001₂ (89₁₀)。许多学生直接相加得到 11000011₂，然后错误地认为没有溢出，因为结果在 8 位内。但在补码表示中，最高位是符号位。两个正数相加必须得到正结果；最高位变为 1 说明结果是负数，因此发生溢出。实际十进制和 195 超出了 8 位有符号整数的最大值 +127，证实溢出。判断法则：同符号数相加，若结果符号不同，则溢出。
01101010₂ + 01011001₂ = 11000011₂ (Overflow)
stion context matters. In processor flags, overflow (V) is set when the carry into the MSB differs from the carry out of the MSB. Here, carry into MSB = 0, carry out = 1, so V = 1. Always check the expected representation before answering.
另一个常见错误是混淆无符号与有符号加法。无符号解释为 195 是正确的，但题目上下文决定答案。在处理器标志中，当最高位的进位输入与进位输出不同时，溢出标志 (V) 置位。此处进位入 MSB 为 0，进位出为 1，故 V=1。答题前务必确认题目要求的表示方式。
2. Normalising Floating Point Binary | 浮点数二进制规格化
A typical mini floating-point format uses 1 sign bit, a 4-bit exponent with a bias of 7, and a 3-bit mantissa that assumes a hidden ‘1’ before the binary point (i.e., the stored mantissa represents 1.m). Problem: represent 0.001101₂ × 2⁴ in this normalised form. A common mistake is to directly place 001101 into the mantissa field, which is incorrect because the mantissa must start with 1. To normalise, shift the binary point right until the first ‘1’ is left of the point: 0.001101₂ × 2⁴ = 1.101₂ × 2¹ nt field therefore stores 1 + 7 = 8 (1000₂). The mantissa field stores the fractional part 101, giving final representation: 0 1000 101.
某微型浮点格式使用 1 位符号、4 位指数（偏移量 7）和 3 位尾数，尾数前隐含一个 ‘1’（即保存的是 1.m 的小数部分）。题目：将 0.001101₂ × 2⁴ 表示为规格化形式。常见错误是将 001101 直接塞入尾数部分，这是错误的，因为尾数必须以 1 开头。要规格化，将小数点右移直到第一个 ‘1’ 出现在小数点左边：0.001101₂ × 2⁴ = 1.101₂ × 2¹（小数点移动 3 位，指数减少 3：4−3=1）。指数域存储 1+7 = 8 (1000₂)。尾数域存小数部分 101，最终得到：0 1000 101。
Many students forget to adjust the exponent after shifting, or they miscalculate the bias. Always remember that normalisation ensures the mantissa is in the form 1.xxxxx, and the exponent must be updated accordingly. Also, if the original number is zero, it should be represented with a special zero pattern (all zeros or agreed convention). Understanding the trade-off between range and precision is key for IB OCR exams.
很多学生移动小数点后忘记调整指数，或者偏移量算错。务必记住，规格化是为了让尾数呈 1.xxxxx 形式，且指数必须同步更新。另外，如果初始数值为零，则需用特殊的全零模式表示。理解范围与精度之间的权衡是 IB 和 OCR 考试的关键。
3. De Morgan’s Laws in Logic Simplification | 德摩根定律在逻辑化简中的应用
Simplify the Boolean expression ¬(A + B) · ¬(C · D). A common error is to apply De Morgan incorrectly and write ¬A · ¬B · ¬C · ¬D. The second term requires careful handling: ¬(C · D) becomes ¬C + ¬D by De Morgan. Therefore the correct expression is (¬A · ¬B) · (¬C + ¬D), which can be left as is or expanded further. Students often miss the change from AND to OR in the second negation. Using a truth table verifies that the original and simplified forms are logically equivalent.
化简布尔表达式 ¬(A + B) · ¬(C · D)。常见错误是错误应用德摩根定律，直接写成 ¬A · ¬B · ¬C · ¬D。第二项需谨慎处理：¬(C · D) 根据德摩根定律应变为 ¬C + ¬D。因此正确结果是 (¬A · ¬B) · (¬C + ¬D)，可以保留或进一步展开。学生经常忽略第二次取反时与运算变为或运算。利用真值表可以验证原表达式和化简后表达式等价。
De Morgan: ¬(X · Y) = ¬X + ¬Y and ¬(X + Y) = ¬X · ¬Y
In logic circuit design, failing to apply these laws correctly can lead to extra gates. Always break down complex negations step by step. Write the rules next to each transformation until you build confidence. Exam questions may also ask for NAND/NOR only implementations, so mastering De Morgan is essential.
在逻辑电路设计中，若不能正确应用这些定律，会引入多余的门。务必一步步分解复合取反。在每一步变换旁边写出所用规则，直到熟练。考试题还可能要求只
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