📚 Logic Gates Exam-Focused Explanation | 逻辑门 考点精讲
Logic gates form the very foundation of digital electronics and computer architecture. Whether you are preparing for IB Computer Science or the WJEC specification, a solid grasp of how these simple yet powerful building blocks work is essential. This article walks you through every key concept, from basic gate behaviour to Boolean algebra and combinational circuit design, with clear explanations, worked examples, and exam tips tailored to both syllabi. By the end, you will be able to confidently analyse truth tables, simplify logic expressions, and interpret circuit diagrams under timed conditions.
逻辑门是数字电子学和计算机体系结构的基石。无论你准备的是 IB 计算机科学还是 WJEC 考试，透彻掌握这些简单而强大的构件都是必不可少的。本文带你梳理每一个关键概念，从基本门的行为到布尔代数和组合电路设计，配有清晰的解释、例题和紧扣两大考纲的应试技巧。学完本文，你将能够在限时条件下信心十足地分析真值表、简化逻辑表达式并解读电路图。
1. The Basic Logic Gates: AND, OR, NOT | 基本逻辑门：与门、或门、非门
sion is written as Q = A · B or simply Q = AB, where the dot symbolises logical conjunction. An OR gate produces a 1 if at least one input is 1; its expression is Q = A + B, with '+' disjunction. The NOT gate, also called an inverter, takes a single input and flips it: Q = ¬A or Q = A'. In circuit diagrams, each gate has a distinct shape – D-shaped symbol for AND, a curved shape for OR, and a triangle with a small circle for NOT – and you must be able to recognise and draw these accurately for the exam.
三种最基本的逻辑门是 AND、OR 和 NOT。AND 门仅在所有输入均为 1 时输出 1；对于两输入端 AND 门，布尔表达式写作 Q = A · B 或直接 Q = AB，点号表示逻辑与。OR 门只要至少一个输入为 1 就输出 1，表达式为 Q = A + B，“+”表示逻辑或。NOT 门也叫反相器，只有一个输入端并将其翻转：Q = ¬A 或 Q = A’。电路图中每种门都有独特的形状——AND 为 D 形符号，OR 为弧形符号，NOT 为带小圆圈的三角——考试中你必须能准确识别和绘制它们。
From a physical perspective, these basic gates are built using transistors. In IB and WJEC, you do not need to design transistor-level circuits, but understanding that a single transistor can act as a NOT gate and that multiple transistors combine to form AND or OR helps reinforce why voltage levels map to logical 0 and 1. The truth tables for AND and OR with two inputs are straightforward, yet they underpin all more complex logic.
从物理层面看，这些基本门由晶体管构成。在 IB 和 WJEC 中，你不需要设计晶体管级电路，但了解单个晶体管可充当 NOT 门、多个晶体管组合构成 AND 或 OR，有助于理解为何用电压高低代表逻辑 0 和 1。两输入 AND 与 OR 的真值表十分简单，但这是所有复杂逻辑的基础。
| A | B | AND (A·B) | OR (A+B) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 |
2. Universal Gates: NAND and NOR | 通用门：与非门和或非门
NAND and NOR gates are termed 'universal' llowed by a NOT: its output is 0 only when all inputs are 1. The Boolean expression is Q = ¬(A · B), often written as Q = (A · B)' is an OR followed by a NOT, outputting 1 only when all inputs are 0; it is written as Q = ¬(A + B) or Q = (A + B)' ier to fabricate with fewer transistors than basic AND/OR gates in certain logic families.
NAND 和 NOR 门被称为“通用门”，因为仅用 NAND 门或仅用 NOR 门就可以实现任何布尔函数。NAND 门是与门后接非门：仅在所有输入为 1 时输出 0，布尔表达式为 Q = ¬(A · B)，常写作 Q = (A · B)’。NOR 门是或门后接非门，仅在所有输入为 0 时输出 1，表达式为 Q = ¬(A + B) 或 Q = (A + B)’。这两种门在半导体制造中应用极广，因为在某些逻辑系列中它们比基本的 AND/OR 门所需晶体管更少，更易于制造。
or instance, to create a NOT from a NAND, you simply tie both inputs together: Q = (A · A)' = A' verter). Practising these transformations is a core skill for both IB Paper 2 and WJEC unit exams.
考题经常要求仅用 NAND 门或仅用 NOR 门构建指定门。例如，用 NAND 实现 NOT：将两个输入端并接，Q = (A · A)’ = A’。类似地，用三个 NAND 可构建 AND：先对两输入做 NAND，再将输出送至第二个 NAND 的两输入端（作反相器用）。反复练习这些转换是 IB 试卷二和 WJEC 单元考试的核心技能。
The NAND truth table complements the AND' inputs (0,0) → 1, (0,1) → 1, (1,0) → 1, (1,1) → 0. The NOR truth table complements the OR' all others → 0. These tables are quick marks in an exam if you can recall them instantly.
NAND 的真值表与 AND 完全相反：输入 (0,0) 输出 1，(0,1) 输出 1，(1,0) 输出 1，(1,1) 输出 0。NOR 的真值表与 OR 相反：(0,0) 输出 1，其余全部输出 0。若能在考场上迅速回忆这些表格，就能轻松拿分。
3. Exclusive-OR (XOR) and Exclusive-NOR (XNOR) | 异或门和同或门
s are 1. For two inputs, this means A is different from B. Its Boolean expression is Q = A ⊕ B, which expands to Q = A·B' + A' te, gives a 1 when both inputs are the same; it is the complement of XOR, written as Q = A ⊙ B or Q = ¬(A ⊕ essential building blocks in arithmetic circuits, such as adders, and in parity checking.
XOR 门（异或门）仅在输入中 1 的个数为奇数时输出 1。对于两输入，意味着 A 与 B 不同。其布尔表达式为 Q = A ⊕ B，可展开为 Q = A·B’ + A’·B。XNOR 门又称同或门，当两输入相同时输出 1，是 XOR 的反相，写作 Q = A ⊙ B 或 Q = ¬(A ⊕ B)。这些门是加法器等算术电路以及奇偶校验的基础构件。
In truth table form, XOR gives 0 for (0,0) and (1,1), and 1 for (0,1) and (1,0). XNOR is the reverse: 1 for (0,0) and (1,1), 0 for the mixed cases. Many students confuse the symbols; in IB and WJEC diagrams, the XOR symbol is an OR gate with an extra curved line on the input side, while XNOR is the same but with a small inversion circle at the output. Always check the label and the truth-table evidence before answering.
在真值表中，XOR 对于 (0,0) 和 (1,1) 输出 0，对于 (0,1) 和 (1,0) 输出 1。XNOR 则相反：(0,0) 和 (1,1) 输出 1，混合情况输出 0。许多学生混淆符号；在 IB 和 WJEC 的图形中，XOR 符号是在 OR 门输入端加一条额外弧线，而 XNOR 同样形状但在输出端加一个小反相圈。作答前务必核实标号及真值表证据。
XOR can be constructed from basic gates: A⊕B = (A+B)·(A·B)' r own, but they frequently appear alongside NAND/NOR in exam problems on logic simplification.
XOR 可用基本门搭建：A⊕B = (A+B)·(A·B)’。识别这种实现有助于在设计题中化简复杂电路。此外，XOR 和 XNOR 门本身不是通用门，但它们常与 NAND/NOR 一同出现在逻辑化简的考题中。
4. Constructing and Interpreting Truth Tables | 构建与解读真值表
A truth table lists every possible combination of input values and the resulting output for a given logic circuit or expression. To construct one, first identify the number of inputs n; the table will have 2ⁿ rows. For each row, evaluate the output column by working through the expression from innermost parentheses outward, or by simulating the circuit gate by gate. This systematic approach eliminates careless mistakes and is especially useful in exams when you are given a complex Boolean expression and must verify which rows yield 1.
真值表列出了给定逻辑电路或表达式的每种可能输入组合及其对应输出。构建方法：首先确定输入个数 n，表格将有 2ⁿ 行。逐行按由内而外的顺序计算表达式的输出，或逐门模拟电路。这种系统化方法能消灭粗心错误，在考试中遇到复杂布尔表达式并需验证哪些行输出 1 时尤其实用。
For example, consider Q = (A·B) + C' listing A, B, C from 000 to 111. Then compute intermediate columns: first find A·B, then C' o order your inputs in standard binary counting order (000, 001, 010, 011, ...). In IB papers, you may be asked to complete a partially filled truth table; in WJEC, you might need to produce the whole table from a given circuit diagram.
例如，考虑 Q = (A·B) + C'。三个输入共 8 行。首先列出 A,B,C 从 000 到 111。然后计算中间列：先求 A·B，再求 C’，最后做或运算。这种分步方法保证准确性。记住真值表的输出列常要求按二进制顺序排列，因此将输入按标准二进制计数顺序排列（000,001,010,011,...）。在 IB 试卷中，可能会要求补全部分真值表；在 WJEC 中，可能需要根据给定电路图自行画出完整真值表。
Another key skill is using a truth table to prove the equivalence of two circuits or two Boolean expressions. If the output columns match for all rows, the expressions are logically equivalent. This is a straightforward method that examiners love to test, so make sure you can complete a truth table quickly and without error.
另一关键技能是利用真值表证明两电路或两布尔表达式的等价性。如果输出列在所有行完全一致，则两者逻辑等价。这是考官爱出的题型，方法直接，因此务必做到快速且无误地完成真值表。
5. Boolean Expressions and Symbolic Representation | 布尔表达式与符号表示
Boolean algebra uses a set of symbols and rules to describe logic functions. The primary operators are AND (· or multiplication), OR (+ or addition), and NOT (overbar ¬ or prime '). Precedence rules apply: NOT takes highest priority, followed by AND, then OR. Thus A + B·C is evaluated as A + (B·C), not (A+B)·C. When an expression includes brackets, they override the default precedence. Being comfortable with this notation is critical for reading exam problems and writing your own simplifications.
布尔代数使用一组符号和规则来描述逻辑功能。主要运算符包括 AND（· 或乘号）、OR（+ 或加号）和 NOT（上划线 ¬ 或撇号 '）。优先级规则为：NOT 最高，其次 AND，最后 OR。因此 A + B·C 应理解为 A + (B·C)，而非 (A+B)·C。若表达式包含括号，括号将覆盖默认优先级。熟练掌握这些符号是读懂考题和书写化简过程的关键。
Alternative notations exist: some textbooks use ∧ for AND, ∨ for OR, and ~ for NOT. IB generally accepts multiple conventions, but the overbar and prime are most common in exam questions. WJEC tends to use the algebra notation with a dot and plus. If you encounter a mixture, just translate mentally. In particular, the overbar across a whole term, like (A+B)•C, means the entire product is inverted; be careful to apply NOT to the entire term, not just the last variable.
还有其它表示法：部分教材用 ∧ 表示 AND，∨ 表示 OR，~ 表示 NOT。IB 通常接受多种习惯，但上划线和撇号在考题中最常见。WJEC 倾向于使用带点号和加号的代数记法。若遇到混合表示，只需在脑中转换。特别注意贯穿整个项的上划线，例如 (A+B)•C 上有一横，表示整个乘积取反；要小心将 NOT 作用于整个项，而非仅作用于最后一个变量。
Equally important is the ability to write a Boolean expression from a logic circuit diagram. Trace the signal path, label intermediate wires, and build the expression step by step. Conversely, given an expression, you should be able to sketch the corresponding gate arrangement. This two-way translation is a favourite for AO2 application and AO3 analysis questions.
同样重要的是从逻辑电路图写出布尔表达式。追踪信号路径，标记中间连线，逐步构建表达式。反过来，给定表达式也应能绘出对应的门排列。这种双向转换是 AO2 应用和 AO3 分析题的常见考点。
6. Combinational Logic Circuit Design | 组合逻辑电路设计
A combinational logic circuit is one where the output depends solely on the current input values, with no memory of past states. Using the basic and universal gates, we can design circuits that realise any given truth table or Boolean function. The design process usually begins by identifying the rows in the truth table that output 1, writing a minterm (a product term where each input appears once in true or complemented form) for each, and then OR-ing all minterms together. This yields the canonical Sum-of-Products (SoP) form, which can then be simplified.
组合逻辑电路是指输出仅取决于当前输入值、对过去状态无记忆的电路。使用基本门和通用门，我们可以设计出实现任意给定真值表或布尔函数的电路。设计流程通常始于找出真值表中输出为 1 的行，为每一行写出一个最小项（每个输入以原变量或反变量形式出现一次的乘积项），再将所有最小项或运算起来，得到规范的积之和 (SoP) 形式，随后可进行化简。
For instance, a circuit that detects when exactly two of three inputs are 1 will have an SoP expression of A'BC + AB'C + ABC'. Once the SoP is obtained, you can apply Boolean algebra laws or Karnaugh maps to minimise the gate count. In exams, you may be asked to design a circuit from a word description: read carefully, extract the conditions, build a truth table, and then derive the simplified expression. This sequence is heavily examined in both IB (Topic 2: Computer Organisation) and WJEC (Unit 1: Digital Technology).
例如，检测三个输入中恰好有两个为 1 的电路，其 SoP 表达式为 A’BC + AB’C + ABC’。得到 SoP 后，可应用布尔代数定律或卡诺图来最小化门数量。考试中可能要求根据文字描述设计电路：仔细阅读，提取条件，建立真值表，再导出简化表达式。该序列在 IB（主题二：计算机组成）和 WJEC（单元一：数字技术）中均考查频繁。
Another common task is to redraw a given circuit using only NAND or only NOR gates. This tests your understanding of universality and De Morgan's laws. The strategy: replace each gate with its NAND-equivalent network, then simplify by removing pairs of series inverters. Methodical practice will make this second nature.
另一常见任务是仅用 NAND 门或仅用 NOR 门重绘给定电路。这考查你对通用性和德摩根定律的理解。策略：将每个门替换为其等价的 NAND 网络，再消去成对串联的反相器。有条不紊地练习可使你游刃有余。
7. Boolean Algebra Laws and Simplification | 布尔代数定律与化简
tity (A+0=A, A·1=A), null (A+1=1, A·0=0), idempotence (A+A=A, A·A=A), complementation (A+A'=1, A·A' ws. The distributive law works both ways: A·(B+C) = A·B + A·C, and A + (B·C) = (A+B)·(A+C) — and expressions much like normal algebra, except for the peculiar second distributive law.
化简逻辑表达式可以减少门数量、降低成本并提升电路速度。基本定律包括：恒等律 (A+0=A, A·1=A)、零律 (A+1=1, A·0=0)、幂等律 (A+A=A, A·A=A)、互补律 (A+A’=1, A·A’=0)，以及交换律、结合律和分配律。分配律双向成立：A·(B+C) = A·B + A·C，并且 A + (B·C) = (A+B)·(A+C)——后者不太直观但同样成立。这些定律让你能像普通代数一样提取或展开表达式，仅有第二条分配律较为特殊。
to arrive at a minimal SoP or minimal Product-of-Sums (PoS) form. A step-by-step approach: ① remove double inversions, ② apply De Morgan's laws to push inversions inward, ③ expand terms if needed, ④ group and eliminate using adjacency (e.g., AB + AB' Practice with past-paper questions teaches you to spot patterns such as redundancy (A + A'B = A + B). Memorising a few standard simplifications saves valuable time during the test.
化简时，目标常是最小化积之和 (SoP) 或和之积 (PoS) 形式。分步方法：① 去除双重取反，② 用德摩根定律将取反向内推，③ 必要时展开项，④ 利用相邻性（如 AB + AB’ = A）合并和消去。练习历年真题能让你学会识别冗余 (A + A’B = A + B) 等模式。熟记几个标准化简能在考试中节约宝贵时间。
It is also essential to check your simplified expression by constructing a truth table for both the original and simplified forms. In high-stakes exams, this verification step can catch errors that algebraic manipulation might introduce, especially when dealing with three or more variables where it is easy to miss a combination.
务必通过为原表达式和化简后表达式分别建立真值表来验证你的化简结果。在紧要考试中，这一验证步骤可发现代数处理可能带来的错误，尤其是处理三个或更多变量时容易漏掉某些组合。
8. De Morgan's Laws and Their Importance | 德摩根定律及其重要性
De Morgan' formation rules that relate AND and OR operations through inversion. The first law states: ¬(A · B) = ¬A + ¬B; the second law: ¬(A + B) = ¬A · ¬ nt of a sum is the product of complements. These laws are not just theoretical curiosities — es, and to pushing inversions into a circuit to allow all-NAND or all-NOR implementations.
德摩根定律是两条通过取反将 AND 和 OR 运算关联起来的转换规则。第一定律：¬(A · B) = ¬A + ¬B；第二定律：¬(A + B) = ¬A · ¬B。换言之，乘积的反等于反的和，和的反等于反的积。这些定律绝非只具理论意义——它们是将 NAND/NOR 与基本门相互转换，以及将反相推入电路以实现全 NAND 或全 NOR 结构的关键。
To apply De Morgan' t as: break the bar over the operation, change the operation sign (· to +, or + to ·), and place bars over the individual variables. In symbolic manipulation, you must also manage double inversions: ¬(¬A) = A. This is why two inverters in series cancel out in a logic circuit.
在电路图中应用德摩根定律：用带反向输入和反向输出的 OR 门替代 AND 门，或反之。许多学生将其形象化为：破开运算上的长划线，改变运算符号（· 变 +，或 + 变 ·），并在各变量上加划线。在符号操作中，还需处理双重取反：¬(¬A) = A。这就是为什么逻辑电路中两个串联的反相器会相互抵消。
Exam questions explicitly targeting De Morgan often ask you to simplify an expression like ¬(A + ¬ hen redraw. Combine De Morgan with other Boolean laws to reduce the final gate count. For instance, starting with Q = ¬(A + ¬ rst tackle the inner negation and work outward, carefully keeping track of each inversion.
明确指向德摩根的试题常要求化简诸如 ¬(A + ¬B) 的表达式，或绘制仅用 NAND 门的等效电路。最稳妥的作答方法是写出初始表达式，逐步应用德摩根，再重绘电路。将德摩根与其他布尔定律结合以减少最终门数。例如，从 Q = ¬(A + ¬(B·C)) 开始，需先处理内部取反再向外推进，仔细跟踪每一次取反。
9. From Gates to Functional Blocks: The Half Adder | 从逻辑门到功能模块：半加器
A half adder is the simplest arithmetic circuit, adding two single-bit binary numbers and producing a sum bit and a carry bit. The sum bit is exactly the XOR of the two inputs (A ⊕ B), and the carry bit is the AND (A·B). Thus, a half adder requires just two gates: one XOR and one AND. Understanding this circuit bridges logic gates and the arithmetic logic unit (ALU) of a processor, a recurrent theme in IB Computer Science Topic 2 and WJEC's digital systems content.
半加器是最简单的算术电路，将两个一位二进制数相加，产生一个和位和一个进位。和位正是两输入的 XOR (A ⊕ B)，进位是 AND (A·B)。因此，一个半加器只需两个门：一个异或门和一个与门。理解该电路架起了逻辑门与处理器算术逻辑单元 (ALU) 之间的桥梁，是 IB 计算机科学主题二和 WJEC 数字系统内容的常见主题。
S = 1 for (0,1) and (1,0). Carry C is 1 only for (1,1). The Boolean expressions are S = A⊕ f adder foundation is where you need to start. Draw the circuit clearly and label S and C.
在真值表中，输入 A、B，和 S 在 (0,0) 和 (1,1) 时为 0，(0,1) 和 (1,0) 时为 1。进位 C 仅在 (1,1) 时为 1。布尔表达式为 S = A⊕B，C = A·B。许多考题进而延伸至全加器（相加三个位：两个操作数加一个进位输入），但半加器是必须打好的基础。清晰绘制电路并标注 S 和 C。
Building a full adder from two half adders and an OR gate is a classic proof of understanding. The sum from the first half adder is XOR-ed again with the carry-in, and the final carry is an OR of the two partial carries. This modular approach illustrates how complex functions are built from simple logic gates, and it aligns with the abstraction principle central to both IB and WJEC syllabi.
用两个半加器和一个或门构建全加器是理解水平的经典证明。第一个半加器的和与进位输入再做异或，最终进位是两个部分进位的或。这种模块化方式展现了如何从简单逻辑门构建复杂功能，且契合 IB 与 WJEC 大纲所强调的抽象化原则。
10. Introduction to Karnaugh Maps for Simplification | 卡诺图化简简介
Karnaugh maps (K-maps) provide a visual method for simplifying Boolean expressions with up to four (or sometimes five) variables. They reorganise the truth table into a grid where adjacent cells differ by exactly one variable, allowing you to spot and combine terms easily. For IB and WJEC, while algebraic simplification is always expected, K-maps are increasingly part of the toolkit, particularly for students aiming for the highest marks in data representation and logic design questions.
卡诺图是一种可视化化简最多四（有时五）个变量的布尔表达式的方法。它将真值表重新组织进一个网格，相邻单元格仅有一个变量取值不同，可以轻松发现并合并项。对 IB 和 WJEC 而言，虽然代数化简始终是必备能力，但卡诺图日益成为工具箱的一部分，尤其是在数据表示和逻辑设计题中想冲击高分的学生。
from the truth table, then circle adjacent groups of 1s in powers of two (1,2,4,8, etc.). Each group corresponds to a product term where the variables that stay constant within the group are kept, and those that change are eliminated. The resulting SoP expression is minimal and often simpler than what manual algebra would yield, especially when terms appear disjoint.
两变量卡诺图为 2×2 网格；三变量为 2×4；四变量为 4×4。根据真值表在格中填入 1 和 0，然后用 2 的幂次方尺寸（1,2,4,8 等）圈出相邻的 1 组。每组对应一个乘积项：保留组内不变的变量，消去变化的变量。得出的 SoP 表达式是最小化的，且通常比手工代数化简更简洁，尤其在各项不相邻时。
K-maps also reveal essential hazards and redundancies, though these are beyond the scope of most introductory exams. However, knowing how to group 1s in the map to obtain the minimum sum-of-products – and to check that your final circuit uses the fewest possible gates – gives you a significant advantage. Typical exam problems give a truth table and ask for the simplest Boolean expression; using a K-map for 3 or 4 inputs is a reliable way to secure full marks.
卡诺图还能揭示必要冒险和冗余，虽然这超出多数入门考试范围。但懂得如何在图中圈 1 以获得最小积之和——并检查最终电路使用了最少门——会给你带来很大优势。典型考题给出真值表，要求写出最简布尔表达式；对三或四输入用卡诺图求解是拿到满分的可靠途径。
11. Exam Tips and Common Mistakes | 考试技巧与常见错误
Exam success in logic gates depends as much on technique as on knowledge. Start by reading the question carefully: underline whether you need to produce a truth table, a Boolean expression, a circuit diagram, or a simplification. Misinterpreting the command word is a frequent slip. When drawing gates, use clear, standard symbols and label all inputs and outputs. Unclear diagrams can lose marks even if the idea is correct.
逻辑门考试的成功既靠知识，也靠技巧。首先认真读题：划出要求是写出真值表、布尔表达式、电路图还是化简结果。误解指令词是常见失误。绘制逻辑门时，使用清晰的标准符号并标注所有输入和输出。潦草模糊的图可能丢分，即便思路正确。
Another pitfall is forgetting that the NOT gate has only one input. In complex circuits, students occasionally draw a NOT gate with two inputs, which is invalid. Also, avoid confusing the OR and AND shapes: the OR has a curved back; the AND has a straight back with a rounded front. In written expressions, don't forget operator precedence – when unsure, use brackets to make your intention explicit.
另一误区是忘记 NOT 门只有一个输入。在复杂电路中，学生偶尔画出带两个输入的 NOT 门，这是无效的。同时，不要混淆 OR 与 AND 的形状：OR 背侧弧形，AND 背侧平直而前部圆润。写表达式时，别忘记运算符优先级——不确定时就用括号明确意图。
When simplifying, always double-check your answer with a quick truth-table mental verification. For a 3-input expression, test a couple of rows that would likely break an incorrect simplification, like 011 or 101. Finally, time management is crucial: Do not spend too long perfecting a single diagram. Allocate roughly one minute per mark, and leave the last five minutes to check for silly errors like missing inversion bubbles.
化简后，务必用快速的心里真
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