📚 Computer Science | Core Exam Points in Computer Architecture | 计算机科学 | 计算机原理核心考点详解
Computer architecture is the foundation of all computer science. Understanding how data flows through the CPU, how memory is organised, and how instructions are executed is essential for any serious computer science student. This guide covers the core exam points in a structured, bilingual format.
计算机原理是整个计算机科学的基石。理解数据如何在 CPU 中流动、存储器如何组织、指令如何被执行，是所有计算机科学学习者的必修课。本指南以结构化、中英对照的形式，系统梳理计算机原理的核心考点。
1. Von Neumann Architecture | 冯·诺依曼架构
The Von Neumann architecture describes a computer system where the program instructions and data are stored in the same memory unit. The CPU fetches instructions from memory, decodes them, and executes them sequentially using a single shared bus for both data and instructions.
冯·诺依曼架构描述了一种计算机系统，其中程序指令和数据存储在同一个存储器中。CPU 从内存中取指令、译码，并通过同一条共享总线依次执行指令和数据操作。
- Single memory space for both instructions and data / 指令与数据共用同一存储空间
- Sequential execution of instructions / 指令按顺序逐条执行
- Shared bus for data, instructions, and control signals / 数据、指令和控制信号共用总线
- Bottleneck: the von Neumann bottleneck – limited throughput between CPU and memory / 瓶颈：冯·诺依曼瓶颈——CPU 与内存之间的有限吞吐量
Key components: the central processing unit (CPU), memory unit, input/output devices, and the system bus. The CPU itself contains the arithmetic logic unit (ALU), the control unit (CU), and registers.
关键组成：中央处理器（CPU）、存储单元、输入/输出设备以及系统总线。CPU 内部包含算术逻辑单元（ALU）、控制单元（CU）和寄存器。
2. The Central Processing Unit (CPU) | 中央处理器
The CPU is the 'brain' of the computer. It is responsible for interpreting and executing instructions. Modern CPUs consist of several key internal components, each with a specific role in the fetch-decode-execute cycle.
CPU 是计算机的“大脑”，负责解释和执行指令。现代 CPU 由多个关键内部组件构成，每个组件在“取指—译码—执行”周期中扮演特定角色。
| Component / 组件 | Function / 功能 |
| ALU (Arithmetic Logic Unit) / 算术逻辑单元 | Performs arithmetic (+, −, ×, ÷) and logical operations (AND, OR, NOT) / 执行算术运算与逻辑运算 |
| CU (Control Unit) / 控制单元 | Directs the operation of the processor, coordinates all activities / 指挥处理器运作，协调所有活动 |
| PC (Program Counter) / 程序计数器 | Holds the address of the next instruction to be executed / 保存下一条待执行指令的地址 |
| MAR (Memory Address Register) / 存储器地址寄存器 | Holds the address of the memory location being accessed / 保存正在访问的内存位置地址 |
| MDR (Memory Data Register) / 存储器数据寄存器 | Holds data being transferred to or from memory / 保存正在传入或传出内存的数据 |
| ACC (Accumulator) / 累加器 | Stores the results of calculations performed by the ALU / 存储 ALU 计算结果的寄存器 |
Exam tip: Be able to identify each register's role and describe what happens to the PC, MAR, MDR, and ACC during each stage of the instruction cycle.
考试提示：必须能够识别每个寄存器的角色，并描述指令周期各阶段中 PC、MAR、MDR 和 ACC 的变化过程。
3. The Fetch-Decode-Execute Cycle | 取指—译码—执行周期
This is the fundamental operational loop of the CPU. Every instruction, regardless of complexity, must pass through these three stages. The cycle repeats continuously from the moment the computer is powered on until it shuts down.
这是 CPU 的基本运行循环。每一条指令，无论复杂与否，都必须经过这三个阶段。从计算机开机到关机，该周期持续循环。
- Fetch 取指：The address in the PC is copied to the MAR. The instruction at that address is loaded into the MDR and then into the current instruction register (CIR). The PC is incremented / PC 中的地址复制到 MAR，该地址中的指令载入 MDR 后送入当前指令寄存器（CIR），PC 自增
- Decode 译码：The CU interprets the instruction to determine the operation to be performed and the operands involved / CU 解释指令以确定要执行的操作及涉及的操作数
- Execute 执行：The ALU or other components carry out the operation. Results are stored in the ACC or written back to memory / ALU 或其他组件执行操作，结果存入 ACC 或写回内存
PC → MAR → Memory → MDR → CIR → Decode → Execute
For exam success, practice drawing a flowchart of this cycle and be able to write a step-by-step description in your own words.
要在考试中取得好成绩，请练习绘制该周期的流程图，并能够用自己的语言写出逐步描述。
4. Registers and the Accumulator | 寄存器与累加器
Registers are extremely fast storage locations located inside the CPU. They hold data temporarily during processing. The size of a register determines how much data the CPU can process at once – commonly 32-bit or 64-bit.
寄存器是位于 CPU 内部的极快存储单元，在处理期间临时保存数据。寄存器的位宽决定了 CPU 一次能处理多少数据——通常为 32 位或 64 位。
The accumulator is a special register that holds the result of the most recent ALU operation. For example, if the CPU performs 5⁺3, the ACC would contain 8 after execution. Understanding ACC is crucial when tracing through assembly code.
累加器是一个特殊寄存器，保存最近一次 ALU 运算的结果。例如，若 CPU 执行 5⁺3，执行后 ACC 将包含 8。理解 ACC 是追踪汇编代码的关键。
Common registers beyond those listed above: the Index Register (IX) for indexed addressing, the Stack Pointer (SP) for stack operations, and the Status Register (SR) storing flag bits.
除上述寄存器外，常见的还有：用于变址寻址的变址寄存器（IX）、用于栈操作的堆栈指针（SP）、以及保存标志位的状态寄存器（SR）。
5. Memory Types and Hierarchy | 存储器类型与层次结构
Memory in a computer system is organised in a hierarchy based on speed, cost, and capacity. Faster memory is more expensive per bit, so systems use a mix to achieve the best balance.
计算机中的存储器按照速度、成本和容量构成层次结构。速度越快的存储器每比特价格越高，因此系统混合使用不同类型以达到最佳平衡。
| Level / 层级 | Type / 类型 | Speed / 速度 | Purpose / 用途 |
| 1 | CPU registers / CPU 寄存器 | Fastest / 最快 | Immediate processing / 即时处理 |
| 2 | Cache (L1, L2, L3) / 缓存 | Very fast / 极快 | Store frequently used data / 存储常用数据 |
| 3 | RAM (Main Memory) / 随机存取存储器 | Fast / 快 | Running programs / 运行中的程序 |
| 4 | ROM / 只读存储器 | Fast / 快 | Booting instructions (non-volatile) / 启动指令（非易失） |
| 5 | Secondary storage (SSD, HDD) / 辅助存储 | Slower / 慢 | Long-term storage / 长期存储 |
Volatile memory loses its contents when power is removed. RAM is volatile. ROM and secondary storage are non-volatile. Know this distinction inside out.
易失性存储器在断电后内容丢失。RAM 是易失性的。ROM 和辅助存储是非易失性的。请务必透彻掌握这一区别。
6. Cache Memory and Virtual Memory | 缓存与虚拟内存
Cache memory is a small, high-speed memory located close to the CPU. It stores copies of frequently accessed data and instructions to reduce the average time to access memory. The principle of locality – both spatial and temporal – explains why caching works so effectively.
缓存是位于 CPU 附近的小容量、高速度存储器。它保存频繁访问的数据和指令副本，以减少平均内存访问时间。局部性原理（空间局部性和时间局部性）解释了缓存的效率来源。
- Temporal locality: the same data is accessed repeatedly over time / 时间局部性：同一数据在短时间内被反复访问
- Spatial locality: nearby memory addresses are likely to be accessed together / 空间局部性：相近的内存地址很可能被一起访问
Virtual memory is a technique that uses secondary storage as an extension of RAM. When RAM is full, less-used pages are moved to a swap file on disk. This allows programs larger than physical RAM to run, but at the cost of speed because disk access is orders of magnitude slower than RAM.
虚拟内存是一种将辅助存储器用作 RAM 扩展的技术。当 RAM 满时，不常用的页面会被移到磁盘上的交换文件中。这使得大于物理内存的程序也能运行，但代价是速度降低，因为磁盘访问比 RAM 慢数个数量级。
Cache hit 命中 → fast access · Cache miss 未命中 → access slower main memory
7. Binary, Hexadecimal, and Two's Complement | 二进制、十六进制与补码
Computers work in binary, but humans find it convenient to use hexadecimal to represent binary patterns. Each hexadecimal digit represents exactly four binary bits, making conversion straightforward.
计算机以二进制工作，但人类使用十六进制来表示二进制模式更为便捷。每个十六进制位精确对应四个二进制位，因此转换非常直接。
0x2F₁₆ = 0010 1111₂ = 47₁₀
Two's complement is the standard method for representing signed integers. To negate a number: invert all bits and add 1. The leftmost bit is the sign bit: 0 for positive, 1 for negative.
补码是表示有符号整数的标准方法。取负数的方法：全部位取反再加 1。最左边一位是符号位：0 表示正数，1 表示负数。
- 8-bit range: −128 to 127 / 8 位范围：−128 至 127
- Overflow occurs when the result exceeds this range / 结果超出此范围时发生溢出
−5₁₀ = 1111 1011₂ (8-bit two's complement)
Practice converting between binary, denary, and hexadecimal fluently. These questions appear in nearly every exam paper.
请熟练练习二进制、十进制和十六进制之间的转换。这类题目几乎出现在每一份考卷中。
8. Logic Gates and Boolean Algebra | 逻辑门与布尔代数
Logic gates are the fundamental building blocks of digital circuits. Each gate implements a Boolean operation. Candidates must know the symbol, truth table, and Boolean expression for each standard gate.
逻辑门是数字电路的基本构建模块。每个门实现一种布尔运算。考生必须掌握每种标准门的符号、真值表和布尔表达式。
| Gate / 门 | Expression / 表达式 | Output = 1 when / 输出为 1 的条件 |
| AND 与门 | A · B | A = 1 AND B = 1 / 两者均为 1 |
| OR 或门 | A ⁺ B | A = 1 OR B = 1 / 至少一个为 1 |
| NOT 非门 | ¬A | A = 0 / 输入为 0 |
| NAND 与非门 | ¬(A · B) | NOT both 1 / 不全是 1 |
| NOR 或非门 | ¬(A ⁺ B) | Neither 1 / 都不是 1 |
| XOR 异或门 | A ⊕ B | A ≠ B / 两者不同 |
Boolean algebra allows the simplification of logic circuits. De Morgan's laws are especially important:
布尔代数用于化简逻辑电路。德摩根定律尤为重要：
¬(A · B) = ¬A ⁺ ¬B · ¬(A ⁺ B) = ¬A · ¬B
Exam questions often ask you to trace signals through a combination of gates or to build a truth table for a given circuit.
考试题常要求你追踪信号经过组合逻辑门，或为给定电路构建真值表。
9. Addressing Modes | 寻址方式
Addressing modes determine how a CPU interprets the operand field of an instruction. Different modes provide different balances between flexibility, range, and speed.
寻址方式决定 CPU 如何解释指令中的操作数字段。不同模式在灵活性、范围和速度之间各有取舍。
- Immediate 立即寻址：The operand is the actual value, e.g., LDA #5 loads the number 5 directly / 操作数就是实际值，例如 LDA #5 直接加载数字 5
- Direct 直接寻址：The operand is the memory address where the value is stored / 操作数是数据存储的内存地址
- Indirect 间接寻址：The operand points to a memory location that contains the address of the actual data – useful for pointers / 操作数指向的内存位置中存有数据的真实地址——适用于指针
- Indexed 变址寻址：The effective address is calculated by adding an index register value to the operand / 有效地址通过将变址寄存器的值与操作数相加得到
Effective address = operand ⁺ index register
Be careful: immediate addressing stores the value itself in the instruction; there is no memory lookup at all.
注意：立即寻址把数值直接存放在指令中，完全不涉及内存查找。
10. Input/Output and Interrupts | 输入输出与中断
I/O devices communicate with the CPU through I/O ports or controllers. There are three primary techniques for managing I/O transfers, each with different trade-offs.
I/O 设备通过 I/O 端口或控制器与 CPU 通信。管理 I/O 传输主要有三种技术，各有权衡。
| Method / 方式 | Description / 描述 | Disadvantage / 缺点 |
| Programmed I/O / 程序控制 I/O | CPU polls device status constantly / CPU 不断查询设备状态 | Wastes CPU time / 浪费 CPU 时间 |
| Interrupt-driven I/O / 中断驱动 I/O | Device signals CPU when ready / 设备就绪时发出中断信号 | Overhead of context switching / 上下文切换的开销 |
| DMA (Direct Memory Access) / 直接存储器访问 | DMA controller transfers data directly to RAM / DMA 控制器直接向 RAM 传输数据 | May conflict with CPU for bus access / 与 CPU 争用总线 |
An interrupt is a signal that causes the CPU to pause its current task, save its state, and execute an interrupt service routine (ISR). After the ISR finishes, the CPU restores the saved state and resumes exactly where it left off.
中断是一种信号，使 CPU 暂停当前任务、保存现场、执行中断服务程序（ISR）。ISR 完成后，CPU 恢复保存的现场，从断点处继续执行。
11. Performance Factors: Clock Speed, Cores, and Pipelining | 性能因素：时钟速度、核心数与流水线
Three main factors determine the speed of a CPU: clock speed, number of cores, and the use of pipelining. Exam questions often ask you to analyse how performance is affected by changing these parameters.
决定 CPU 速度的三个主要因素：时钟频率、核心数量和流水线的使用。考试题经常要求你分析这些参数变化对性能的影响。
- Clock speed (measured in Hz) sets the number of fetch-decode-execute cycles per second / 时钟频率（以 Hz 计量）决定每秒取指—译码—执行周期数
- Multi-core processors allow true parallel execution of multiple threads / 多核处理器支持多个线程的真正并行执行
- Pipelining overlaps the stages of different instructions, so while one instruction is being executed, the next is being decoded, and the one after is being fetched / 流水线使不同指令的各个阶段重叠——当一条指令在执行时，下一条正在译码，再下一条正在取指
Performance = clocks per second × instructions per clock
However, performance is not perfectly scalable: increasing clock speed is limited by heat generation, and multiple cores do not help with purely sequential programs.
然而，性能并非完美线性扩展：提升时钟频率受限于发热，而多核对纯串行程序并无帮助。
12. Common Exam Mistakes and How to Avoid Them | 常见考试错误及规避方法
Students lose marks not because they lack knowledge, but because they make repetitive, avoidable errors. Here are the most frequent ones to watch for in computer architecture papers.
学生失分往往不是因为知识不足，而是因为反复出现可避免的错误。以下是在计算机原理试卷中最常见的几类问题。
- Confusing MAR and MDR – MAR holds an address, MDR holds data / 混淆 MAR 和 MDR——MAR 保存的是“地址”，MDR 保存的是“数据”
- Forgetting that RAM is volatile while ROM is non-volatile / 忘记 RAM 易失而 ROM 非易失
- Writing the truth table for XOR when the question asks for XNOR / 将异或门真值表当作同或门来写
- Using hexadecimal letters (A–F) instead of binary digits in machine code tracing / 在机器码追踪中使用十六进制字母而不是二进制数字
- Not distinguishing between the instruction cycle (fetch, decode, execute) and the machine instruction cycle (fetch phase, indirect phase, execute phase, interrupt phase) / 未区分指令周期与机器指令周期
The best strategy: practise past papers, memorise the truth tables until they are automatic, and write definitions using precise technical vocabulary.
最佳策略：刷历年真题、将真值表记忆到条件反射的程度，并使用精确的技术词汇写出定义。
The core of computer architecture can be learned with systematic practice. Master the CPU cycle, memory hierarchy, data representation, and logic gates, and the exam becomes predictable rather than intimidating.
计算机原理的核心知识可以通过系统练习来掌握。熟练 CPU 周期、存储层次、数据表示和逻辑门后，考试将变得可预测而不再令人生畏。
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