📚 OCR AS Computer Science Year 1: Core Concepts and Exam Skills | OCR 计算机科学第一年核心概念与考试技能
This revision guide covers the OCR AS Computer Science Year 1 specification, including the CPU, data representation, operating systems, networks, algorithms and the legal and ethical context.
本复习指南覆盖 OCR AS 计算机科学第一年考试大纲，包括 CPU、数据表示、操作系统、网络、算法以及法律与伦理背景。
The aim is not simply to list definitions but to connect each concept to the way OCR writes its questions, so that you can move from "I know the term" to "I can score the marks".
本文的目的不只是罗列定义，而是把每个概念与 OCR 的出题方式对应起来，让你从"我知道这个词"升级为"我能拿到分"。
1. The CPU and Von Neumann Architecture | CPU 与冯·诺依曼架构
OCR expects you to describe the role of the control unit (CU), arithmetic logic unit (ALU), registers and buses in a Von Neumann architecture. The stored program concept means instructions and data share the same memory, so the CPU treats both as binary values.
OCR 要求你描述控制单元（CU）、算术逻辑单元（ALU）、寄存器以及总线在冯·诺依曼架构中的作用。存储程序概念意味着指令和数据共享同一内存，因此 CPU 将二者都视为二进制值。
The control unit decodes each instruction and directs the flow of data around the processor, generating timing and control signals. The ALU performs arithmetic operations such as addition and subtraction, and logical operations such as AND, OR, NOT and shifts. The accumulator holds the output of the ALU, while status flags record properties of the last result.
控制单元对每条指令进行译码，指挥数据在处理器内部流动，并生成时序与控制信号。ALU 执行加法、减法等算术运算，以及 AND、OR、NOT 和移位等逻辑运算。累加器保存 ALU 的输出，状态标志则记录上一次结果的属性。
A key exam point is that Von Neumann architecture uses a single set of buses shared by instructions and data, which creates the Von Neumann bottleneck. Harvard architecture separates instruction memory from data memory and is common in embedded systems and digital signal processors.
一个关键考点是：冯·诺依曼架构只有一组总线，由指令和数据共用，从而产生"冯·诺依曼瓶颈"。哈佛架构把指令存储与数据存储分开，常见于嵌入式系统和数字信号处理器中。
| Component | 部件 | Role | 作用 |
|---|---|
| Control Unit | 控制单元 | Decodes instructions, sends control signals, keeps timing | 译码指令、发出控制信号、维持时序 |
| ALU | 算术逻辑单元 | Carries out arithmetic and logical operations | 执行算术与逻辑运算 |
| Registers | 寄存器 | Small, extremely fast on-chip storage | 位于芯片内、容量小但速度极快的存储 |
| Buses | 总线 | Carry addresses, data and control signals | 传输地址、数据与控制信号 |
2. Registers, Buses and the Stored Program Concept | 寄存器、总线与存储程序概念
Key registers are the program counter (PC), memory address register (MAR), memory data register (MDR), current instruction register (CIR) and accumulator (ACC). Buses include the address bus, data bus and control bus.
关键寄存器包括程序计数器（PC）、内存地址寄存器（MAR）、内存数据寄存器（MDR）、当前指令寄存器（CIR）和累加器（ACC）。总线包括地址总线、数据总线和控制总线。
- PC | 程序计数器: holds the address of the next instruction to be fetched | 保存下一条待取指令的地址
- MAR | 内存地址寄存器: holds the address currently being read from or written to | 保存当前要读取或写入的内存地址
- MDR | 内存数据寄存器: holds the data just read, or the data about to be written | 保存刚读出的数据，或即将写入的数据
- CIR | 当前指令寄存器: holds the instruction currently being decoded and executed | 保存当前正在译码与执行的指令
- ACC | 累加器: holds the result of ALU operations | 保存 ALU 运算的结果
The address bus is one-directional because the CPU only sends addresses outwards. The data bus is bidirectional because data travels both to and from memory. The control bus is bidirectional and carries read and write signals, clock pulses and interrupt requests.
地址总线是单向的，因为 CPU 只向外发送地址。数据总线是双向的，因为数据在内存与 CPU 之间双向传输。控制总线也是双向的，承载读/写信号、时钟脉冲和中断请求。
5,536 unique locations. The width of the data bus determines the word size and therefore how much data can be transferred in a single operation.
地址总线的宽度决定了可寻址的内存容量。16 位地址总线可以寻址 2¹⁶ = 65,536 个不同位置。数据总线的宽度决定字长，也就决定了单次操作可以传输多少数据。
3. The Fetch-Decode-Execute Cycle | 取指-译码-执行周期
The fetch-decode-execute cycle is the sequence of steps the CPU repeats endlessly while a program runs. OCR frequently asks for the register transfers at each stage, so practise writing them rather than describing them loosely in words.
取指-译码-执行周期是 CPU 在程序运行期间不断重复的步骤序列。OCR 经常要求写出每一阶段的寄存器传送过程，因此要练习写出寄存器之间的传送关系，而不是用含糊的语言描述。
- Fetch | 取指: the address in the PC is copied to the MAR; the instruction is fetched from memory into the MDR; the MDR content is copied to the CIR; the PC is incremented | PC 中的地址复制到 MAR；指令从内存取到 MDR；MDR 内容复制到 CIR；PC 自增
- Decode | 译码: the CU splits the instruction into opcode and operand and determines what must happen | CU 将指令拆分为操作码和操作数，判断需要执行什么操作
- Execute | 执行: the operation is carried out, which may involve the ALU, further memory access or an I/O operation | 执行运算，可能涉及 ALU、进一步的内存访问或输入输出操作
An important detail is that the PC is incremented during the fetch stage, not after execution. This is why the cycle can continue without confusion about which instruction comes next.
一个重要细节是：PC 在取指阶段就自增，而不是在执行之后。这正是该周期能够持续进行而不会弄错下一条指令的原因。
Interrupts are checked at the end of the execute stage. If a higher-priority interrupt is waiting, the current register contents are pushed onto the stack, the interrupt service routine (ISR) address is loaded into the PC, and the cycle resumes from that new address.
中断在"执行"阶段结束后被检查。如果存在优先级更高的中断，当前寄存器内容会被压入栈中，中断服务例程（ISR）的地址被载入 PC，随后周期从该新地址继续运行。
4. CPU Performance and System Performance | CPU 性能与系统性能
Candidates must be able to explain how clock speed, number of cores, cache size and pipeline depth affect performance, and also explain the limits of each factor.
考生必须能够解释时钟速度、核心数量、缓存大小和流水线深度如何影响性能，同时也要说明每种因素的局限。
- Clock speed | 时钟速度: measured in hertz; more cycles per second means more instructions completed per second, assuming everything else is equal | 以赫兹计量；在其它条件相同时，每秒周期数越多，每秒完成的指令越多
- Number of cores | 核心数量: allows genuine parallel execution of independent processes | 允许相互独立的进程真正并行执行
- Cache size | 缓存大小: keeps frequently used instructions and data close to the CPU, reducing the slow trip to main memory | 把常用指令与数据保留在 CPU 附近，减少访问主存的缓慢往返
- Pipeline depth | 流水线深度: overlaps the fetch, decode and execute stages of different instructions | 让不同指令的取指、译码、执行阶段相互重叠
A common exam trap is to claim that doubling the number of cores doubles performance. Software must be written to be parallelisable, and the tasks must be genuinely independent; otherwise the extra cores sit idle waiting for shared data.
常见的考试陷阱是声称核心数翻倍性能就翻倍。软件必须可并行化，且任务必须真正独立；否则额外核心只会空转等待共享数据。
Cache memory is faster than RAM but far more expensive per byte, which is why the hierarchy exists: registers, then cache, then RAM, then virtual memory on the disk.
缓存的存取速度快于内存，但每字节成本高得多，这正是存储层级存在的原因：寄存器 → 缓存 → 内存 → 磁盘上的虚拟内存。
5. Data Representation: Binary, Hexadecimal and Units | 数据表示：二进制、十六进制与单位
OCR expects fluency in converting between denary, binary and hexadecimal, and in performing binary addition and shifts without a calculator.
OCR 要求你熟练地在十进制、二进制和十六进制之间转换，并能不用计算器完成二进制加法与移位。
Denary to binary: divide by 2 repeatedly and read the remainders upwards
十进制转二进制：反复除以 2，将余数自下而上读出
Hexadecimal is used because it is far shorter for humans to read than binary, and each hex digit maps exactly to four bits, so conversion is mechanical. A 16-bit value becomes a four-digit hex value.
使用十六进制是因为它比二进制短得多、更便于人阅读，而且每个十六进制位正好对应四位二进制，转换是机械性的。16 位数值恰好写成四位十六进制数。
| Unit | 单位 | Value | 数值 |
|---|---|
| Bit | 位 | A single 0 or 1 | 单个 0 或 1 |
| Nibble | 半字节 | 4 bits | 4 位 |
| Byte | 字节 | 8 bits | 8 位 |
| Kibibyte | 千字节（二进制） | 2¹⁰ = 1024 bytes | 2¹⁰ = 1024 字节 |
| Mebibyte | 兆字节（二进制） | 2²⁰ = 1,048,576 bytes | 2²⁰ = 1,048,576 字节 |
| Gibibyte | 吉字节（二进制） | 2³⁰ bytes | 2³⁰ 字节 |
A shift left by one place multiplies a binary value by 2 and a shift right divides by 2. Left shifts can cause overflow when the result needs more bits than are available, and this is a very commonly examined consequence.
二进制数左移一位相当于乘以 2，右移一位相当于除以 2。当结果需要的位数超过可用位数时，左移会导致溢出，这是非常常见的考点。
Unsigned range for n bits = 0 to (2ⁿ − 1)
n 位无符号整数范围 = 0 到 (2ⁿ − 1)
6. Representing Characters, Images and Sound | 字符、图像与声音的表示
Character sets convert symbols into binary codes. ASCII uses 7 bits and covers 128 characters; extended ASCII uses 8 bits and covers 256. Unicode uses variable-length encoding and can represent essentially every writing system, which is why emoji and non-Latin scripts appear correctly on modern devices.
字符集把符号转换为二进制编码。ASCII 使用 7 位，覆盖 128 个字符；扩展 ASCII 使用 8 位，覆盖 256 个。Unicode 采用可变长度编码，几乎可以表示所有书写体系，这也是现代设备能正确显示表情符号和非拉丁文字的原因。
Bitmapped images are stored as a grid of pixels, each with a binary code for its colour. Resolution is the number of pixels wide multiplied by the number high. Colour depth is the number of bits used per pixel.
位图图像以像素网格存储，每个像素用二进制代码表示颜色。分辨率是水平像素数乘以垂直像素数。色深是每个像素使用的位数。
Image file size (bits) = width × height × colour depth
图像文件大小（位）= 宽 × 高 × 色深
Sound is stored by sampling. The height of the analogue wave is measured at regular intervals and each measurement is rounded to the nearest available value, which is why quantisation error and loss of quality occur.
声音通过采样存储。每隔固定时间测量模拟波形的高度，并把每次测量值取整到最接近的可用值，这正是量化误差和音质损失产生的原因。
Sound file size (bits) = sample rate × bit depth × number of channels × duration
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