📚 Computer Architectures and the Fetch–Execute Cycle | 计算机体系结构与取指–执行周期
A computer is able to run programs only because its hardware and software cooperate through a repeating sequence known as the fetch–execute cycle. Understanding this cycle, the components of the central processing unit and the buses that connect them is central to Cambridge Computer Science.
计算机能够运行程序，是因为硬件和软件通过一个不断重复的序列——取指–执行周期——协同工作。理解这一周期、中央处理器的组成部分以及连接它们的总线，是剑桥计算机科学的核心内容。
1. What Is Computer Architecture? | 什么是计算机体系结构
Computer architecture describes the structure and behaviour of a computer system as seen by the programmer, including the CPU, memory, input/output devices and the ways they communicate.
计算机体系结构描述程序员所看到的计算机系统的结构和行为，包括 CPU、存储器、输入/输出设备以及它们之间的通信方式。
In the Cambridge syllabus, architecture focuses on the organisation of the processor, its registers and the fetch–execute cycle rather than on physical electronics.
在剑桥大纲中，体系结构重点关注处理器的组织、寄存器以及取指–执行周期，而不是物理电子电路。
2. The Stored-Program Concept and Von Neumann Model | 存储程序概念与冯·诺依曼模型
The von Neumann model stores both program instructions and data in the same main memory. This stored-program concept means a computer can be reprogrammed simply by changing the contents of memory.
冯·诺依曼模型将程序指令和数据存储在同一个主存储器中。这种存储程序概念意味着只需改变存储器内容即可对计算机重新编程。
A single set of buses and a single memory are used for both instructions and data, which creates the well-known von Neumann bottleneck when the CPU waits for memory access.
指令和数据共用一组总线和同一个存储器，这就产生了著名的冯·诺依曼瓶颈——CPU 必须等待存储器访问。
3. The Processor: Control Unit and ALU | 处理器：控制单元与算术逻辑单元
The central processing unit, or CPU, contains two main parts: the control unit and the arithmetic logic unit. The control unit decodes instructions and sends timing and control signals to coordinate all other components.
中央处理器（CPU）包含两个主要部分：控制单元和算术逻辑单元。控制单元译码指令并发出定时和控制信号，以协调所有其他部件。
The arithmetic logic unit carries out arithmetic operations such as addition and subtraction, as well as logic operations such as AND, OR and NOT. Results are usually placed in the accumulator.
算术逻辑单元执行加法、减法等算术运算，以及 AND、OR、NOT 等逻辑运算。结果通常放入累加器中。
4. Registers: The CPU's Immediate Memory | 寄存器：CPU 的立即存储器
Registers are extremely fast memory locations inside the CPU. The Cambridge specification expects you to know the program counter, memory address register, memory data register, current instruction register and accumulator.
寄存器是 CPU 内部极快的存储单元。剑桥大纲要求你了解程序计数器、存储器地址寄存器、存储器数据寄存器、当前指令寄存器和累加器。
The program counter holds the address of the next instruction to be fetched. It is automatically incremented or changed when a jump instruction occurs.
程序计数器存放下一条将要取出的指令地址。它会自动递增，或者在遇到跳转指令时被改变。
The MAR stores the address being accessed in memory. The MDR stores the data or instruction that has been read from or is to be written to memory.
MAR 存储正在访问的存储器地址。MDR 存储从存储器读出或将要写入存储器的数据或指令。
5. Buses: Address, Data and Control | 总线：地址总线、数据总线和控制总线
A bus is a set of parallel wires that carries signals between components. The CPU uses three main buses: the address bus, the data bus and the control bus.
总线是一组并行导线，在部件之间传输信号。CPU 使用三种主要总线：地址总线、数据总线和控制总线。
The address bus is unidirectional from the CPU to memory and carries the location to be accessed. The data bus is bidirectional and carries instructions or data. The control bus carries timing and read/write signals.
地址总线是从 CPU 到存储器的单向总线，传送要访问的地址。数据总线是双向的，传送指令或数据。控制总线传送定时和读/写信号。
6. The Fetch Stage | 取指阶段
The fetch stage begins the cycle. The contents of the program counter are copied to the memory address register, so the CPU knows which address to read from memory.
取指阶段开始整个周期。程序计数器的内容被复制到存储器地址寄存器，使 CPU 知道要从哪个地址读取。
The CPU sends a read signal along the control bus and places the address on the address bus. Main memory then returns the instruction along the data bus into the memory data register.
CPU 通过控制总线发送读信号，并将地址放到地址总线上。主存储器随后通过数据总线将指令返回到存储器数据寄存器中。
The instruction is copied from the MDR into the current instruction register, and the program counter is incremented so that it points to the next instruction.
指令从 MDR 复制到当前指令寄存器，程序计数器递增，使其指向下一条指令。
7. The Decode Stage | 译码阶段
During the decode stage, the control unit examines the instruction held in the current instruction register. It splits the instruction into the operation code, or opcode, and the operand, which may be data or an address.
在译码阶段，控制单元检查当前指令寄存器中的指令。它将指令分为操作码和操作数，操作数可以是数据或地址。
The control unit then produces the internal signals needed to carry out that particular operation. For example, an ADD instruction activates the ALU addition circuit.
然后控制单元产生执行该特定操作所需的内部信号。例如，ADD 指令会激活 ALU 的加法电路。
8. The Execute Stage | 执行阶段
In the execute stage, the processor carries out the operation specified by the opcode. If the instruction requires data from memory, the CPU may need to read or write using the MAR and MDR again.
在执行阶段，处理器执行操作码规定的操作。如果指令需要从存储器读取数据，CPU 可能需要再次使用 MAR 和 MDR 进行读或写。
Arithmetic and logic operations take place in the ALU. The result is often stored in the accumulator or written back to a memory location.
算术和逻辑运算在 ALU 中进行。结果通常存储在累加器中，或者写回到某个存储器地址。
Once execution is complete, the cycle repeats from the fetch stage unless a halt instruction stops the processor or an interrupt changes the flow.
执行完成后，周期从取指阶段重新开始，除非停机指令使处理器停止，或中断改变了流程。
9. A Step-by-Step Fetch–Execute Example | 取指–执行周期实例
Consider a simple stored program that adds two numbers. The instruction LDA 23 means load the contents of address 23 into the accumulator, ADD 24 means add the contents of address 24 to the accumulator, and STO 25 means store the accumulator result in address 25.
考虑一个简单的存储程序，它把两个数相加。指令 LDA 23 表示将地址 23 的内容装入累加器，ADD 24 表示将地址 24 的内容与累加器相加，STO 25 表示将累加器结果存入地址 25。
For LDA 23, the fetch stage copies the instruction into the CIR and increments the PC. The decode stage identifies LDA as 'load accumulator from a memory address'. The execute stage places 23 on the address bus, reads the data value into the MDR and copies it into the accumulator.
对于 LDA 23，取指阶段将指令复制到 CIR 并递增 PC。译码阶段识别出 LDA 是“从存储器地址装入累加器”。执行阶段将 23 放到地址总线上，将数据值读入 MDR，并复制到累加器中。
ADD 24 and STO 25 follow the same fetch–decode–execute pattern. This repetitive sequence is exactly how a CPU moves through a whole program.
ADD 24 和 STO 25 遵循相同的取指–译码–执行模式。这个重复序列正是 CPU 逐条执行整个程序的方式。
10. Clock Speed, Cores and Cache | 时钟速度、核心数与缓存
Clock speed measures the number of cycles per second, usually in gigahertz. A higher clock speed can complete more fetch–execute cycles each second, but it also generates more heat and uses more power.
时钟速度衡量每秒的周期数，通常以千兆赫兹为单位。较高的时钟速度每秒可以完成更多取指–执行周期，但也会产生更多热量并消耗更多电能。
A processor with multiple cores contains more than one processing unit, so several instructions can be processed in parallel. However, software must be written to make use of multiple cores.
具有多个核心的处理器包含多个处理单元，因此可以并行处理多条指令。但是，软件必须经过编写才能利用多个核心。
Cache is a small amount of very fast memory located close to or inside the CPU. It stores frequently used instructions and data, reducing the number of slow accesses to main memory.
缓存是靠近或位于 CPU 内部的一小块高速存储器。它存放经常使用的指令和数据，从而减少对主存储器的缓慢访问次数。
11. Instruction Sets and Their Impact | 指令集及其影响
An instruction set is the collection of all machine instructions a CPU can execute. Each instruction has an opcode that states the operation and an operand that gives the data or address to use.
指令集是 CPU 能够执行的全部机器指令的集合。每条指令都有一个说明操作的操作码和一个给出数据或地址的操作数。
Processors with different instruction sets may not run the same machine code. This is why a program compiled for one architecture often cannot run directly on another architecture.
具有不同指令集的处理器可能无法运行相同的机器代码。这就是为一种体系结构编译的程序通常不能直接在另一种体系结构上运行的原因。
12. Embedded Systems and Alternative Architectures | 嵌入式系统与替代体系结构
An embedded system is a computer built into a larger device to perform a dedicated function, such as a washing machine controller, engine management unit or digital thermometer. It usually has limited memory and low power consumption.
嵌入式系统是嵌入在更大设备中执行专用功能的计算机，例如洗衣机控制器、发动机管理单元或数字温度计。它通常内存有限、功耗较低。
Some embedded systems use a Harvard architecture, which stores instructions and data in separate memories and uses separate buses. This allows instruction and data fetches to occur at the same time and can improve performance in dedicated applications.
一些嵌入式系统使用哈佛体系结构，它将指令和数据存放在独立的存储器中并使用独立总线。这使指令和数据的读取可以同时进行，并能提高专用应用的性能。
Although the Cambridge course focuses on the von Neumann model, recognising that alternative architectures exist helps explain why different systems suit different tasks.
虽然剑桥课程以冯·诺依曼模型为主，但认识到替代体系结构的存在有助于解释为什么不同系统适合不同任务。
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