📚 End of Unit 4: Exam-style Case Study Questions | 单元4末：考试风格案例研究题
For Cambridge International A-Level Computer Science, Unit 4 typically covers Processor Fundamentals, including CPU architecture, the fetch-decode-execute cycle, assembly language, and interrupts. This article presents exam‑style case study questions that mirror the types of scenarios you might face in Paper 3 or Paper 4, with detailed worked solutions to consolidate your understanding.
针对剑桥国际A-Level计算机科学，单元4通常涵盖处理器原理，包括CPU架构、取指-解码-执行循环、汇编语言和中断。本文提供考试风格的案例研究题目，模拟你在试卷3或试卷4中可能遇到的场景，并附有详细的解答，以巩固理解。
1. Case Study 1: A Basic 8-bit RISC Processor | 案例研究1：一个基本的8位RISC处理器
A simplified RISC CPU has four general-purpose registers R0 to R3, a program counter (PC), an instruction register (IR), a memory address register (MAR), a memory data register (MDR), and an accumulator (ACC). Main memory is byte-addressable with 8-bit words. Instructions are also 8 bits wide. The instruction set includes LOAD, STORE, ADD, SUB, JUMP, and HALT.
一个简化的RISC CPU有四个通用寄存器R0至R3、程序计数器（PC）、指令寄存器（IR）、内存地址寄存器（MAR）、内存数据寄存器（MDR）以及累加器（ACC）。主存按字节寻址，字长8位。指令也是8位宽。指令集包括LOAD、STORE、ADD、SUB、JUMP和HALT。
2. Question 1(a) – Register Transfers During Fetch | 问题1(a) – 取指期间的寄存器传送
Explain the sequence of register transfers that takes place during the fetch phase of the instruction cycle. In your answer, refer to the roles of the PC, MAR, MDR, and IR.
解释指令周期取指阶段发生的寄存器传送序列。在你的回答中，需提及PC、MAR、MDR和IR的作用。
Solution: The PC holds the address of the next instruction. Its contents are copied to the MAR. A memory read signal is sent, and the instruction at that address is placed into the MDR. The instruction is then transferred from the MDR to the IR. Meanwhile, the PC is incremented by 1 to point to the subsequent instruction.
解答：PC保存下一条指令的地址。其内容被复制到MAR。发送内存读信号，该地址处的指令被放入MDR。然后将指令从MDR传送到IR。同时，PC递增1，指向下一条指令。
3. Question 1(b) – Assembly Language and Machine Code | 问题1(b) – 汇编语言与机器码
The opcode for LOAD is 0001, and the operand field specifies a source register. The instruction LOAD R2 copies the contents of register R2 into the ACC. Write the 8-bit machine code for the instruction, assuming the register code for R2 is 10 in binary.
LOAD的操作码为0001，操作数字段指定源寄存器。指令LOAD R2将寄存器R2的内容复制到ACC。写出该指令的8位机器码，假设R2的寄存器代码为二进制10。
by register code (2 bits) and two unused bits (00). Thus: 0001 10 00 = 00011000 in binary.
解答：8位指令格式：操作码（4位）后跟寄存器代码（2位）和两个未使用位（00）。因此：0001 10 00 = 二进制00011000。
4. Question 1(c) – Pipeline Hazard | 问题1(c) – 流水线冲突
The processor uses a three-stage pipeline: Fetch, Decode, Execute. Consider the following two instructions in sequence: ADD R1 (add the value in R1 to the ACC) and STORE R1 (store the ACC value into the address held in R1). Identify the pipeline hazard that occurs and explain how it can be resolved.
该处理器使用三级流水线：取指、解码、执行。考虑以下两条连续指令：ADD R1（将R1中的值加到ACC）和STORE R1（将ACC值存储到R1所存地址中）。识别发生的流水线冲突，并解释如何解决。
Solution: A data hazard (read-after-write) occurs because the ADD instruction writes a new value to the ACC in the Execute stage, but the following STORE uses the old ACC value if decoded simultaneously. This can be resolved by inserting a pipeline bubble (stall) or by forwarding the result from the Execute stage directly to the Decode stage of the next instruction.
解答：发生数据冲突（写后读），因为ADD指令在执行阶段向ACC写入新值，但下一条STORE如果同时解码则会使用旧的ACC值。这可以通过插入流水线气泡（停顿）来解析，或通过将执行阶段的结果直接转发到下一条指令的解码阶段
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