📚 IGCSE Edexcel Computer Science: CPU Key Points Explainer | IGCSE Edexcel 计算机科学：CPU 考点精讲
The Central Processing Unit (CPU) is often called the 'brain' of the computer. For IGCSE Edexcel Computer Science, you need to understand its purpose, the Von Neumann architecture, how instructions are executed, and the factors that affect performance. This article breaks down every key concept into bite-sized, bilingual explanations to help you master the topic.
中央处理器（CPU）常被称为计算机的“大脑”。对于 IGCSE Edexcel 计算机科学，你需要理解它的用途、冯·诺依曼架构、指令如何执行以及影响性能的因素。本文将所有关键概念拆解为中英双语的精讲，帮你彻底掌握这一考点。
1. Introduction to CPU and Von Neumann Architecture | CPU 简介与冯·诺依曼架构
The CPU is the hardware component that carries out the instructions of a computer program. It processes data by performing fetch-decode-execute cycles. Nearly all modern CPUs follow the Von Neumann architecture, where both program instructions and data are stored in the same memory. This stored-program concept allows a computer to be flexible and perform many different tasks by simply loading new programs.
CPU 是执行计算机程序指令的硬件组件，通过取指-解码-执行周期来处理数据。几乎所有现代 CPU 都遵循冯·诺依曼架构，即程序指令和数据存放在同一个存储器中。这种“存储程序”概念让计算机变得灵活，只需加载新程序就能完成各种任务。
- Shared memory for instructions and data / 指令和数据共用存储器
- Uses a set of registers to hold temporary values / 使用一组寄存器暂存数据
- Components communicate via buses / 组件通过总线通信
2. Components of the CPU: Control Unit | CPU 的组件：控制单元
The Control Unit (CU) is the component that directs the operation of the processor. It decodes the instruction fetched from memory and sends control signals to coordinate the other parts of the CPU and memory. The CU does not execute the instruction itself – it tells the ALU, registers, and memory what to do.
控制单元（CU）是指导处理器运行的组件。它解码从内存中取出的指令，并发送控制信号来协调 CPU 其他部分及内存的工作。CU 本身不执行指令，而是告诉 ALU、寄存器和内存该做什么。
- Generates timing signals / 生成时序信号
- Controls the flow of data between CPU and memory / 控制 CPU 与内存之间的数据流
- Decodes instructions into micro-operations / 将指令解码为微操作
3. Components of the CPU: Arithmetic Logic Unit (ALU) | CPU 的组件：算术逻辑单元
The Arithmetic Logic Unit (ALU) carries out all the mathematical calculations and logical operations. It can perform addition, subtraction, multiplication, division, and bitwise logic operations like AND, OR, and NOT. The ALU receives operands from registers, processes them, and stores the result back into the accumulator or another register.
算术逻辑单元（ALU）负责执行所有算术运算和逻辑运算，包括加、减、乘、除以及 AND、OR、NOT 等位逻辑操作。ALU 从寄存器接收操作数，处理后将结果存回累加器或其他寄存器。
- Handles integer arithmetic and logic / 处理整数运算和逻辑
- Result affects flag bits (e.g., zero, carry) / 结果影响标志位（如零标志、进位标志）
- Works closely with the accumulator / 与累加器紧密配合
4. Registers: Program Counter, Accumulator, MAR, MDR | 寄存器：程序计数器、累加器、存储器地址寄存器、存储器数据寄存器
The CPU contains a small number of fast storage locations called registers. The most important ones for IGCSE are: Program Counter (PC) holds the address of the next instruction to be fetched; Accumulator (ACC) stores intermediate arithmetic/logic results; Memory Address Register (MAR) holds the address of the memory location to be read/written; Memory Data Register (MDR) holds the actual data or instruction that has been read from or is about to be written to memory.
CPU 内部有少量高速存储位置，称为寄存器。IGCSE 最重要的四个寄存器是：程序计数器（PC）存放下一条要取指令的地址；累加器（ACC）存放算术/逻辑运算的中间结果；存储器地址寄存器（MAR）存放欲读/写的内存地址；存储器数据寄存器（MDR）存放从内存读出或将要写入内存的实际数据或指令。
| Register | Function |
| PC | Points to next instruction / 指向下一条指令 |
| ACC | Stores immediate results / 存立即结果 |
| MAR | Holds memory address / 存内存地址 |
| MDR | Holds data/instruction from/to memory / 存数据/指令 |
5. The Fetch-Decode-Execute Cycle | 取指-解码-执行周期
This is the fundamental process by which the CPU operates. It runs continuously while the computer is on. The steps are: Fetch – the address from the PC is copied to the MAR, the instruction at that address is read from memory into the MDR, and the PC is incremented. Decode – the CU interprets the instruction held in the MDR. Execute – the CU sends signals to carry out the instruction, possibly involving the ALU or memory read/write. The cycle then repeats.
这是 CPU 运行的基本流程，电脑开机时它持续运行。步骤为：取指 — PC 中的地址被复制到 MAR，该地址的指令从内存读入 MDR，然后 PC 自增；解码 — CU 解释 MDR 中的指令；执行 — CU 发送信号执行指令，可能涉及 ALU 或内存读写。之后循环重复。
- PC → MAR → Read memory → MDR → Instruction decoded → Executed
- Each cycle takes a fixed number of clock ticks / 每个周期占用固定数量的时钟节拍
- The speed depends on the clock frequency / 速度取决于时钟频率
6. Buses: Data, Address, and Control | 总线：数据总线、地址总线与控制总线
Buses are the communication pathways between the CPU and memory (and I/O devices). The data bus carries the actual information (instructions or data) in both directions. The address bus carries memory addresses from the CPU to memory; it is unidirectional. The control bus carries control signals (e.g., read, write, clock) from the CU to coordinate components. The width of these buses affects system performance.
总线是 CPU 与内存（及 I/O 设备）之间的通信通道。数据总线双向传输实际信息（指令或数据）；地址总线单向将内存地址从 CPU 传向内存；控制总线传输控制信号（如读、写、时钟），由 CU 发出以协调各组件。这些总线的宽度会影响系统性能。
- Wider data bus = more bits transferred per clock cycle / 数据总线越宽，每时钟周期传输位数越多
- Wider address bus = larger addressable memory space / 地址总线越宽，可寻址的内存空间越大
- Control bus coordinates everything / 控制总线协调所有操作
7. CPU Performance Factors: Clock Speed | CPU 性能影响因素：时钟速度
Clock speed, measured in Hertz (Hz), indicates how many fetch-decode-execute cycles the CPU can complete per second. A processor with a higher clock speed (e.g., 3.5 GHz) can execute more instructions per second than one with a lower speed (e.g., 2.0 GHz), assuming all other factors are equal. However, overheating and power consumption increase with higher clock speeds.
时钟速度，以赫兹（Hz）为单位，表示 CPU 每秒可完成的取指-解码-执行周期数。时钟速度较高的处理器（如 3.5 GHz）在同等条件下每秒执行的指令数比较低速度（如 2.0 GHz）的多。但更高的时钟速度也带来发热和功耗的增加。
- 1 GHz = 10⁹ cycles per second / 10⁹ 个周期/秒
- Doubling clock speed does not always double performance / 速度翻倍并不总意味着性能翻倍
- Limited by thermal and electrical constraints / 受散热和电气限制
8. CPU Performance Factors: Number of Cores | CPU 性能影响因素：核心数量
A core is a complete independent processing unit that can run its own fetch-decode-execute cycle. A multi-core processor (dual-core, quad-core, etc.) can work on multiple tasks simultaneously (true parallelism) or split a single task if the software supports it. More cores improve multitasking and can speed up parallel applications, but not all software is designed to use multiple cores efficiently.
核心是一个独立的完整处理单元，可运行自己的取指-解码-执行周期。多核处理器（双核、四核等）能同时处理多个任务（真正的并行），或在软件支持时将单个任务拆分处理。更多核心能够提升多任务处理能力并加速并行应用程序，但并非所有软件都能高效利用多核。
- Each core runs at the same clock speed / 每个核心运行在相同的时钟速度
- Operating system must schedule tasks across cores / 操作系统需要在各核间调度任务
- Some tasks are sequential and cannot be split / 部分任务为串行，无法拆分
9. CPU Performance Factors: Cache Memory | CPU 性能影响因素：高速缓存
Cache is a small amount of very fast memory located on or near the CPU. It stores frequently accessed instructions and data so the CPU does not have to fetch them from slower RAM every time. A larger cache typically means a higher hit rate, reducing the average memory access time and improving overall performance. Modern CPUs often have multiple levels of cache (L1, L2, L3).
缓存是位于 CPU 内部或附近的小容量高速存储器，存放频繁使用的指令和数据，避免 CPU 每次都从较慢的 RAM 中读取。更大的缓存通常意味着更高的命中率，减少平均内存访问时间，从而提升整体性能。现代 CPU 通常有多级缓存（L1, L2, L3）。
- L1 cache is the fastest but smallest / L1 缓存最快但容量最小
- L2 and L3 are progressively larger and slower / L2、L3 容量递增但速度递减
- Cache misses force a slower RAM access / 缓存未命中则需较慢的 RAM 访问
10. Embedded Systems and their CPUs | 嵌入式系统及其 CPU
An embedded system is a computer system built into a larger device to perform a dedicated function. The CPU inside an embedded system is often a microcontroller with reduced power and performance compared to a general-purpose CPU, optimised for the specific task. Examples include washing machines, digital cameras, microwave ovens, and car engine management systems. They are typically low-cost, low-power, and highly reliable.
嵌入式系统是嵌入到更大的设备中执行专用功能的计算机系统。其内部的 CPU 通常是一个微控制器，功耗和性能低于通用 CPU，并针对特定任务优化。例子包括洗衣机、数码相机、微波炉和汽车发动机管理系统。它们通常成本低、功耗低且可靠性高。
- Runs a single program or firmware / 运行单一程序或固件
- Limited user interface or none / 用户界面有限或没有
- Cannot be reprogrammed easily by the user / 用户不易重新编程
- Processors are often ARM-based for efficiency / 处理器常用 ARM 架构以提高效率
11. Common Exam Question Pitfalls | 常见考题易错点
Students often confuse MAR with MDR: MAR stores the address, MDR stores the data. Another mistake is saying the clock speed directly equals the number of instructions per second – in reality, some instructions take multiple cycles. When describing the fetch cycle, do not forget that the PC increments during the fetch, not after. Also, explain why embedded systems usually do not need a general-purpose OS.
学生常混淆 MAR 与 MDR：MAR 存地址，MDR 存数据。另一个错误是说时钟速度直接等于每秒执行指令数——实际上有些指令需要多个周期。描述取指周期时，不要忘记 PC 在取指过程中自增，而非之后。还要解释为什么嵌入式系统通常不需要通用操作系统。
- MAR = Memory Address Register, MDR = Memory Data Register
- Clock speed in Hz ≠ Instructions per second / 时钟速度 ≠ 每秒指令数
- PC is incremented during the fetch stage / PC 在取指阶段自增
- Embedded systems: no need for a full OS or user apps / 无需完整操作系统或用户应用
12. Summary of Key Points | 考点总结
A quick recap for revision: the CPU follows the Von Neumann architecture and comprises CU, ALU, and registers. The fetch-decode-execute cycle is the engine. Performance is determined by clock speed, number of cores, and cache size; no single factor works in isolation. Embedded systems are specialist CPUs with a single purpose. Master these concepts and you will be well prepared for any IGCSE Edexcel exam question on the CPU.
快速复习总结：CPU 遵循冯·诺依曼架构，由控制单元、算术逻辑单元和寄存器组成。取指-解码-执行周期是核心引擎。性能由时钟速度、核心数和缓存大小共同决定，没有单一因素能独立起效。嵌入式系统是专用于单一目的的处理器。掌握这些概念，足以应对 IGCSE Edexcel 有关 CPU 的任何考题。
Published by TutorHao | Computer Science Revision Series | aleveler.com
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