📚 IGCSE Edexcel Computer Architecture: Key Revision Notes | IGCSE Edexcel 计算机体系结构 考点精讲
Computer architecture forms the backbone of the IGCSE Edexcel Computer Science syllabus. It describes how the central processing unit (CPU) and memory work together to execute instructions, and it covers the fundamental principles behind the fetch-decode-execute cycle, system buses, and processor performance. Mastering this topic is essential for both multiple-choice and longer-answer questions, as concepts often reappear in data representation, programming, and networking units.
计算机体系结构是IGCSE Edexcel计算机科学课程的基石。它描述了中央处理器(CPU)与存储器如何协同工作以执行指令，并涵盖了取指-译码-执行周期、系统总线以及处理器性能背后的基本原理。掌握这一主题对选择题和长答题都至关重要，因为这些概念经常在数据表示、编程和网络等单元中反复出现。
1. Von Neumann Architecture | 冯·诺依曼体系结构
Almost all modern computers are based on the Von Neumann architecture, which stores both program instructions and data in the same main memory. This design means that the CPU reads instructions and data through the same buses, allowing a program to be easily modified by treating instructions as data. The key characteristic is a single, unified memory space that holds both the program and the data it manipulates.
几乎所有现代计算机都基于冯·诺依曼体系结构，该结构将程序指令和数据存储在同一个主存储器中。这种设计意味着CPU通过相同的总线读取指令和数据，通过把指令当作数据，程序可以被轻易修改。其关键特征是一个统一的存储器空间，同时存放程序及其操作的数据。
- The CPU contains a control unit, an arithmetic logic unit, and registers.
- CPU包含控制单元、算术逻辑单元和寄存器。
- Memory stores both instructions and data in binary form.
- 存储器以二进制形式同时存储指令和数据。
- Instructions are fetched one at a time, decoded, and executed sequentially.
- 指令被逐一取出、译码并顺序执行。
2. CPU Components: ALU, CU, and Registers | CPU组件：算术逻辑单元、控制单元和寄存器
The CPU is divided into three main functional areas. The arithmetic logic unit (ALU) performs arithmetic operations (addition, subtraction) and logical operations (AND, OR, NOT). The control unit (CU) directs the flow of data and instructions, sending control signals to coordinate all components. Registers are extremely fast, small storage locations within the CPU used to hold data, addresses, or instructions temporarily during processing.
CPU分为三个主要功能区。算术逻辑单元(ALU)执行算术运算（加法、减法）和逻辑运算（AND、OR、NOT）。控制单元(CU)指挥数据和指令的流动，发送控制信号以协调所有组件。寄存器是CPU内部极快的小型存储位置，用于在处理期间临时存放数据、地址或指令。
- The ALU only works on data; it does not decide what to do.
- ALU只处理数据，它不决定要做什么。
- The CU uses a clock signal to keep everything synchronised.
- CU使用时钟信号使所有操作同步。
- General-purpose registers can hold any data; special-purpose registers have fixed roles.
- 通用寄存器可存放任何数据；专用寄存器有固定职责。
3. Key Registers: PC, MAR, MDR, ACC | 关键寄存器：程序计数器、存储器地址寄存器、存储器数据寄存器、累加器
Several special-purpose registers drive the fetch-decode-execute cycle. The program counter (PC) holds the memory address of the next instruction to be fetched. The memory address register (MAR) holds the address of the memory location being read from or written to. The memory data register (MDR) holds the actual data or instruction that has been read from memory or is about to be written. Finally, the accumulator (ACC) temporarily stores the results of ALU operations.
几个专用寄存器驱动着取指-译码-执行周期。程序计数器(PC)保存下一条要取出指令的存储器地址。存储器地址寄存器(MAR)保存正在被读写的内存单元地址。存储器数据寄存器(MDR)保存从内存读出或即将写入内存的实际数据或指令。最后，累加器(ACC)暂时存放ALU的运算结果。
| Register | 寄存器 | Role | 作用 |
|---|---|---|---|
| PC | 程序计数器 | Points to next instruction | 指向下一条指令 |
| MAR | 存储器地址寄存器 | Holds the address being accessed | 存放正被访问的地址 |
| MDR | 存储器数据寄存器 | Holds the data/instruction moved | 存放移动的数据/指令 |
| ACC | 累加器 | Stores ALU results temporarily | 暂存ALU结果 |
4. The System Buses: Data, Address, and Control | 系统总线：数据总线、地址总线和控制总线
Buses are sets of parallel wires that carry information between the CPU and other components. The address bus is unidirectional and carries the location of the memory or I/O device to be accessed. The data bus is bidirectional, moving actual instructions or data between processor and memory. The control bus carries command signals, such as read, write, and clock signals, to synchronise operations.
总线是一组并行导线，在CPU与其他组件之间传递信息。地址总线是单向的，携带要访问的内存或I/O设备的位置。数据总线是双向的，在处理器和内存之间传送实际指令或数据。控制总线携带诸如读、写和时钟等命令信号，以同步操作。
- The width of the address bus determines the maximum number of addressable memory locations.
- 地址总线的宽度决定了可寻址内存单元的最大数量。
- A wider data bus allows more bits to be moved at once, improving performance.
- 更宽的数据总线允许一次传输更多位，提升性能。
- The control bus includes lines for memory read, memory write, and interrupt requests.
- 控制总线包括存储器读、存储器写和中断请求等线路。
5. The Fetch-Decode-Execute Cycle | 取指-译码-执行周期
Every instruction the CPU processes goes through the same three-step cycle. In the fetch step, the address in the PC is copied to the MAR, a read signal is sent, and the instruction is moved into the MDR. In the decode step, the control unit interprets the instruction and prepares the ALU and registers for execution. In the execute step, the actual operation is carried out — data may be loaded from memory, written back, or an arithmetic calculation may be performed — and the PC is incremented to point to the next instruction.
CPU处理的每一条指令都经历相同的三步周期。在取指阶段，PC中的地址被复制到MAR，发送读信号，指令被移入MDR。在译码阶段，控制单元解释指令并让ALU和寄存器准备好执行。在执行阶段，实际操作被执行——可能从内存加载数据、写回结果或完成算术运算——并且PC递增，指向下一条指令。
- The PC is incremented before the next fetch begins, unless a jump instruction alters it.
- PC在下次取指开始前递增，除非跳转指令改变了它的值。
- In modern CPUs, pipelining allows overlapping of fetch, decode, and execute phases.
- 在现代CPU中，流水线技术允许取指、译码和执行阶段重叠进行。
- The cycle repeats billions of times per second in a fast processor.
- 在高速处理器中，该周期每秒重复数十亿次。
6. Factors Affecting CPU Performance: Clock Speed | 影响CPU性能的因素：时钟速度
Clock speed, measured in hertz, indicates how many cycles the CPU can complete each second. A 3.5 GHz processor can theoretically execute 3.5 billion cycles per second. Higher clock speeds generally mean faster processing because instructions can be fetched and executed more quickly. However, clock speed is not the only factor; modern CPUs also generate more heat at higher frequencies, requiring better cooling solutions.
时钟速度以赫兹为单位，表示CPU每秒可完成的周期数。一个3.5 GHz的处理器理论上每秒可执行35亿个周期。更高的时钟速度通常意味着更快的处理速度，因为指令可以更快地取出和执行。然而，时钟速度并非唯一因素；现代CPU在更高频率下也会产生更多热量，需要更好的冷却方案。
Doubling the clock speed does not always double performance because other bottlenecks, such as memory latency, may restrict the overall speed. The relationship is often expressed as:
加倍时钟速度并不总能带来性能翻倍，因为内存延迟等其他瓶颈可能限制整体速度。关系常表示为：
Execution Time ∝ 1 / Clock Frequency
7. Factors Affecting CPU Performance: Cores and Cache | 影响CPU性能的因素：核心数与缓存
A multi-core processor contains two or more independent processing units on one chip. Each core can run its own fetch-decode-execute cycle, so multiple tasks can truly run in parallel. However, software must be written to distribute the workload across cores; not all tasks can be parallelised. Adding cores greatly improves multitasking and performance in designed applications like video editing.
多核处理器在一个芯片上包含两个或更多独立处理单元。每个核心可运行自己的取指-译码-执行周期，因此多个任务可以真正并行运行。然而，软件必须被编写为能将负载分配到各个核心；并非所有任务都能并行化。增加核心可极大地改善多任务处理及在视频编辑等设计好的应用中的性能。
Cache is a small, ultra-fast memory inside the CPU that stores frequently used instructions and data. Level 1 (L1) cache is the fastest and smallest, often built per core. Level 2 (L2) is slightly slower but larger, and Level 3 (L3) is shared among cores. Having more cache reduces the number of times the CPU must access slower main memory (RAM), significantly speeding up execution.
缓存是CPU内部一种超快的小型存储器，存放频繁使用的指令和数据。一级缓存(L1)最快且最小，通常每个核心独享。二级缓存(L2)稍慢但更大，三级缓存(L3)在核心间共享。拥有更多缓存可减少CPU必须访问较慢主存(RAM)的次数，显著提升执行速度。
- A dual-core processor is not automatically twice as fast as a single-core at the same frequency.
- 相同频率下，双核处理器不会自动比单核快一倍。
- Cache hits happen when the required data is found in the cache; a miss requires fetching from RAM.
- 当所需数据在缓存中找到时发生缓存命中；未命中则需要从RAM取数据。
8. Cache Memory: Levels and Function | 缓存：级别与功能
Modern CPUs use a hierarchy of caches to keep the processor supplied with data. L1 cache is split into instruction cache and data cache, and it runs at the speed of the CPU core. L2 cache is larger, typically a few hundred kilobytes to several megabytes per core. L3 cache is shared by all cores and serves as a last-level buffer before accessing main memory. This hierarchy balances speed and cost, because faster memory is more expensive to manufacture.
现代CPU使用缓存层级结构来保证处理器持续获得数据。L1缓存分为指令缓存和数据缓存，并以CPU核心的速度运行。L2缓存更大，通常每个核心有几百KB到几MB。L3缓存由所有核心共享，是访问主存前的最后一级缓冲。这种层级结构平衡了速度与成本，因为更快的存储器制造成本更高。
When the CPU needs data, it checks L1 first, then L2, then L3, and finally RAM. Effective cache management, including prefetching algorithms, predictively loads instructions before they are requested. Cache size and latency directly influence benchmark scores and real-world responsiveness in IGCSE questions.
当CPU需要数据时，它先检查L1，然后L2，再L3，最后是RAM。有效的缓存管理，包括预取算法，会在指令被请求之前预测性地加载它们。在IGCSE考题中，缓存大小和延迟直接影响基准测试分数和实际响应速度。
9. Embedded Systems | 嵌入式系统
An embedded system is a computer built into a larger device to perform a dedicated function. Unlike general-purpose desktops, it typically runs a single program stored in ROM. Examples include microwave ovens, washing machines, digital watches, and car engine management systems. These systems are often based on microcontrollers that integrate a simple CPU, memory, and input/output peripherals on one chip.
嵌入式系统是内置在更大设备中执行特定功能的计算机。与通用桌面电脑不同，它通常运行一个存储在ROM中的单一程序。例子包括微波炉、洗衣机、电子表和汽车发动机管理系统。这些系统通常基于微控制器，将简单CPU、存储器和输入/输出外设集成在一个芯片上。
- Embedded systems are optimised for low power consumption, reliability, and real-time responses.
- 嵌入式系统针对低功耗、高可靠性和实时响应进行了优化。
- Firmware, the software on an embedded device, is rarely changed by the user.
- 固件是嵌入式设备上的软件，用户很少改变它。
- In the exam, you may be asked to compare embedded systems with general-purpose computers.
- 考试中可能要求比较嵌入式系统与通用计算机。
10. Exam Tips & Common Pitfalls | 应考技巧与常见陷阱
ores result. Do not forget to mention that the PC increments. Confusing MAR and MDR is a common mistake: MAR holds the address, while MDR holds the data. Also, make sure you can clearly distinguish between the roles of the address bus, data bus, and control bus.
在解释取指-译码-执行周期时，始终按正确顺序说出寄存器：PC → MAR → MDR → CU译码 → ALU执行 → ACC存储结果。不要忘记提及PC递增。混淆MAR和MDR是常见错误：MAR存放地址，而MDR存放数据。此外，确保能清晰区分地址总线、数据总线和控制总线的作用。
For performance factors, link each one to a concrete effect. For example, 'a higher clock speed means more cycles per second, so the fetch-decode-execute cycle can repeat more often' rather than just saying 'it makes it faster'. When discussing cache, emphasise that it stores frequently accessed instructions and data to reduce average memory access time. Use technical vocabulary precisely to gain full marks in extended responses.
对于性能因素，将每一个与具体效果联系起来。例如，“更高的时钟速度意味着每秒更多周期，因此取指-译码-执行周期可更频繁地重复”，而不只是说“它使它更快”。讨论缓存时，强调它存储频繁访问的指令和数据以降低平均存储器访问时间。准确使用技术词汇，在扩展回答中获得满分。
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