Year 12 AQA Computer Science: Unit Test Mock Paper Analysis | AQA 计算机科学 Year 12 单元测试模拟卷解析

📚 Year 12 AQA Computer Science: Unit Test Mock Paper Analysis | AQA 计算机科学 Year 12 单元测试模拟卷解析

Mock exams are vital for Year 12 students preparing for the AQA AS Computer Science exams. They help identify strengths and weaknesses, familiarise you with the exam format, and build confidence under timed conditions. This article walks you through a typical unit test mock paper, explaining the answers and the reasoning behind them, covering key topics from data representation to system software.

模拟考试对于准备 AQA AS 计算机科学考试的 Year 12 学生至关重要。它们有助于发现优势与不足，熟悉考试形式，并在计时条件下建立信心。本文将讲解一份典型的单元测试模拟卷，解释答案及其推理过程，涵盖从数据表示到系统软件的关键主题。

1. Data Representation and Two's Complement | 数据表示与二进制补码

Question: Represent the denary number -37 in 8-bit two's complement. Show your steps and verify the result.

题目：将十进制数 -37 表示为 8 位二进制补码。写出步骤并验证结果。

First, write the positive number 37 in 8-bit binary. 37 is 32 + 4 + 1, which gives 00100101.

首先，写出正数 37 的 8 位二进制。37 为 32 + 4 + 1，因此是 00100101。

Next, invert all the bits (flip 0 to 1 and 1 to 0) to obtain the one's complement: 11011010.

接着，将所有位取反（0 变 1，1 变 0）得到反码：11011010。

Then add 1 to the one's complement to get the two's complement: 11011010 + 1 = 11011011. So -37 in 8-bit two's complement is 11011011.

然后在反码上加 1 得到补码：11011010 + 1 = 11011011。因此 -37 的 8 位二进制补码为 11011011。

We can verify: the two' he remaining bits 1011011 equal 91 in denary (64+16+8+2+1). -128 + 91 = -37, which is correct.

我们可以验证：负数补码的值等于 -128 加上剩余位的数值。对于 11011011，最高位为 1（表示负数），剩余位 1011011 十进制为 91（64+16+8+2+1）。-128 + 91 = -37，结果正确。

The table below summarises the conversion steps.

下表总结了转换步骤。

Step	Action	Result
1	Write +37 in 8-bit binary	00100101
2	Invert bits (one's complement)	11011010
3	Add 1	11011011
4	Two's complement (final)	11011011

Understanding two's complement is essential for representing negative integers and performing subtraction in a computer's ALU.

理解二进制补码对于表示负整数以及在计算机的算术逻辑单元中执行减法至关重要。

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2. Logic Gates and Boolean Simplification | 逻辑门与布尔化简

Question: Simplify the Boolean expression ¬(A ∧ B) ∧ (A ∨ B) using Boolean laws and then draw the corresponding logic circuit using only NAND gates.

题目：使用布尔定律化简表达式 ¬(A ∧ B) ∧ (A ∨ B)，然后仅使用与非门绘制相应的逻辑电路。

Step 1: Apply De Morgan's Law to ¬(A ∧ B). This becomes ¬A ∨ ¬B. So the expression becomes (¬A ∨ ¬B) ∧ (A ∨ B).

第一步：对 ¬(A ∧ B) 应用德摩根定律，得到 ¬A ∨ ¬B。因此表达式变为 (¬A ∨ ¬B) ∧ (A ∨ B)。

Treat this as a conjunction of two disjunctions. Distribute using the distributive law: (¬A ∨ ¬B) ∧ (A ∨ B) = (¬A ∧ A) ∨ (¬A ∧ B) ∨ (¬B ∧ A) ∨ (¬B ∧ B).

第二步：将其看作两个析取项的合取。使用分配律展开：(¬A ∨ ¬B) ∧ (A ∨ B) = (¬A ∧ A) ∨ (¬A ∧ B) ∨ (¬B ∧ A) ∨ (¬B ∧ B)。

Step 3: Simplify terms. (¬A ∧ A) is always false (0), and (¬B ∧ B) is also false. So we are left with (¬A ∧ B) ∨ (¬B ∧ A). This is exactly the XOR operation: A ⊕ B.

第三步：化简各项。(¬A ∧ A) 恒为假 (0)，(¬B ∧ B) 也恒为假。因此剩下 (¬A ∧ B) ∨ (¬B ∧ A)，这正是异或运算：A ⊕ B。

The simplified expression is A ⊕ B. This can be implemented using four NAND gates: first NAND(A,A)= ¬A, NAND(B,B)= ¬B, then NAND(A, ¬B) and NAND(¬ AND of those two outputs. In practice, XOR is a fundamental logic function used in adders.

简化后的表达式为 A ⊕ B。这可以用四个与非门实现：首先 NAND(A,A) = ¬A，NAND(B,B) = ¬B，然后 NAND(A, ¬B) 和 NAND(¬A, B)，最后对这两个输出做与非运算。实际上，异或是一种用于加法器的基本逻辑函数。

The following truth table confirms the equivalence:

下面的真值表证实了等价性：

A	B	A ⊕ B	¬(A ∧ B) ∧ (A ∨ B)
0	0	0	0
0	1	1	1
1	0	1	1
1	1	0	0

This skill is tested often in the AQA paper, requiring both algebraic manipulation and circuit interpretation.

这一技能在 AQA 试卷中经常考查，既要求代数运算又要求电路分析。

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3. CPU Architecture and the FDE Cycle | CPU 体系结构与取指-译码-执行周期

Question: Describe the steps of the fetch-decode-execute (FDE) cycle in a von Neumann architecture processor, and explain the role of the program counter (PC), memory address register (MAR), memory data register (MDR), and current instruction register (CIR).

题目：描述冯·诺依曼架构处理器中取指-译码-执行 (FDE) 周期的步骤，并解释程序计数器 (PC)、内存地址寄存器 (MAR)、内存数据寄存器 (MDR) 和当前指令寄存器 (CIR) 的作用。

Fetch phase: The PC holds the address of the next instruction. This address is copied to the MAR, and the control unit sends a read signal to memory. The instruction at that address is fetched from RAM and placed into the MDR. Then it is moved to the CIR. Meanwhile, the PC is incremented by 1 (or the length of the instruction) to point to the next instruction.

取指阶段：PC 保存下一条指令的地址。该地址被复制到 MAR，控制单元向内存发送读信号。该地址处的指令从 RAM 中取出并放入 MDR，然后传送到 CIR。同时，PC 加 1（或指令长度）以指向下一条指令。

Decode phase: The control unit examines the CIR and splits the instruction into opcode and operand. It determines what operation is required (e.g., ADD, LOAD) and identifies the operands or addresses involved.

译码阶段：控制单元检查 CIR 并将指令分解为操作码和操作数。它确定需要什么操作（例如 ADD、LOAD）并识别相关的操作数或地址。

Execute phase: The control unit activates the appropriate components to carry out the instruction. For an arithmetic instruction, the ALU performs the calculation; for a memory access, another fetch or write operation may occur using the MAR and MDR. After execution, the cycle repeats unless a HALT instruction is encountered.

执行阶段：控制单元激活相应组件来执行指令。对于算术指令，ALU 执行计算；对于内存访问，可能会使用 MAR 和 MDR 进行另一次取指或写入操作。执行完毕后，重复该周期，除非遇到 HALT 指令。

The speed of the cycle depends on the clock frequency. Modern CPUs use pipelining to overlap stages and improve performance, but the fundamental FDE cycle remains the core of program execution.

周期的速度取决于时钟频率。现代 CPU 使用流水线技术重叠各个阶段以提高性能，但基本的 FDE 周期仍然是程序执行的核心。

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4. Assembly Language and Addressing Modes | 汇编语言与寻址模式

Question: A processor has an instruction set that includes LDA (load accumulator), ADD, STA (store accumulator), and HLT. Write an assembly program that adds two numbers stored in memory locations 10 and 11, and stores the result in location 12. Explain how immediate and direct addressing are used.

题目：某处理器的指令集包含 LDA（加载累加器）、ADD、STA（存储累加器）和 HLT。编写一个汇编程序，将存储在内存地址 10 和 11 的两个数相加，并将结果存入地址 12。解释立即寻址和直接寻址的用法。

The program using direct addressing:

使用直接寻址的程序：

LDA 10
ADD 11
STA 12
HLT

Explanation: LDA 10 loads the value from memory location 10 into the accumulator. ADD 11 adds the value from location 11 to the accumulator. STA 12 stores the result in location 12. HLT stops the processor.

解释：LDA 10 将内存地址 10 中的值加载到累加器。ADD 11 将地址 11 中的值与累加器相加。STA 12 将结果存入地址 12。HLT 停止处理器。

Direct addressing means the operand is the address of the data. Immediate addressing, in contrast, would have the data itself embedded in the instruction. For example, if the instruction set supported it, 'LDA #5' would load the immediate value 5 into the accumulator. Immediate addressing is faster but less flexible because the value is fixed.

直接寻址意味着操作数是数据所在的地址。相比之下，立即寻址将数据本身嵌入指令中。例如，如若指令集支持，'LDA #5' 会将立即值 5 加载到累加器。立即寻址速度更快，但因为值是固定的，灵活性较差。

When the program is assembled, each instruction is converted into a numeric opcode and operand, stored in memory. The FDE cycle then executes these machine code instructions sequentially.

当程序被汇编后，每条指令被转换为数字操作码和操作数并存储在内存中。然后 FDE 周期顺序执行这些机器码指令。

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5. Programming Concepts and Pseudocode Trace | 编程概念与伪代码跟踪

Question: Consider the following pseudocode:

题目：考虑以下伪代码：

x ← 3
y ← 10
WHILE x < y
   x ← x + 2
   y ← y - 1
ENDWHILE
OUTPUT x

Complete a trace table showing the values of x and y after each iteration, and state the final output.

完成一个跟踪表，显示每次迭代后 x 和 y

Published by TutorHao | Year 12 Computer Science Revision Series | aleveler.com

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