📚 A-Level Edexcel CS: Logic Gates Revision | A-Level Edexcel 计算机：逻辑门考点精讲
Logic gates are the fundamental building blocks of digital circuits. In the Edexcel A-Level Computer Science specification, you are expected to understand the function of basic and derived gates, analyse and design combinational logic circuits, apply Boolean algebra and Karnaugh maps for simplification, and construct adders, multiplexers and flip-flops. This article summarises the key revision points.
逻辑门是数字电路的基本构建模块。在Edexcel A-Level计算机科学大纲中，你需要理解基本门和衍生门的功能，分析和设计组合逻辑电路，应用布尔代数和卡诺图进行化简，并构建加法器、多路复用器和触发器。本文总结了关键考点。
1. Basic Logic Gates (AND, OR, NOT) | 基本逻辑门 (AND, OR, NOT)
st one input is 1, given by Q = A + B. A NOT gate (inverter) outputs the complement, Q = A'. Symbols and truth tables are shown below.
有三种基本逻辑门：AND、OR和NOT。与门仅在所有输入均为1时输出1，布尔表达式为 Q = A · B。或门只要至少一个输入为1就输出1，表示为 Q = A + B。非门（反相器）输出补码 Q = A'。符号和真值表如下。
| A | B | AND Q | OR Q |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 |
NOT gate truth table is straightforward: input A = 0 gives Q = 1; input A = 1 gives Q = 0.
非门真值表很简单：输入 A = 0 时 Q = 1；输入 A = 1 时 Q = 0。
2. NAND and NOR Gates | NAND 和 NOR 门
d by a NOT. Its output is 1 unless all inputs are 1. The Boolean expression is Q = (A · B)' an OR followed by a NOT; output is 1 only when all inputs are 0, expressed as Q = (A + B)'. Both are considered universal gates.
与非门是与门后接非门。除非所有输入均为1，否则输出为1。布尔表达式为 Q = (A · B)'。或非门是或门后接非门；仅当所有输入均为0时输出为1，表达式为 Q = (A + B)'。两者都被视为通用门。
| A | B | NAND Q | NOR Q |
|---|---|---|---|
| 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
3. Exclusive-OR (XOR) and Exclusive-NOR (XNOR) | 异或 (XOR) 和同或 (XNOR) 门
The XOR gate outputs 1 when its inputs differ. Its Boolean expression is Q = A ⊕ B. The XNOR gate (equivalence) outputs 1 when inputs are equal, written as Q = (A ⊕ B)' or Q = A ⊙ B. XOR is fundamental for arithmetic circuits such as adders.
异或门在输入不同时输出1，布尔表达式为 Q = A ⊕ B。同或门（相等）在输入相同时输出1，写作 Q = (A ⊕ B)' 或 Q = A ⊙ B。XOR是加法器等算术电路的基础。
| A | B | XOR Q | XNOR Q |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
4. Truth Tables and Boolean Expressions | 真值表与布尔表达式
or a circuit with output 1 for inputs (A,B) = (0,1) and (1,0), the SOP expression is Q = A'B + AB', which is exactly XOR.
每个逻辑电路都可以用真值表描述，列出所有输入组合及其对应输出。布尔表达式可以通过对最小项求和（SOP）或对最大项求积（POS）得到。例如，一个电路在输入 (A,B) = (0,1) 和 (1,0) 时输出1，其SOP表达式为 Q = A'B + AB'，这正是异或运算。
When analysing a given logic diagram, work from inputs to output, writing the expression at each gate's output. Then combine to form the overall expression and simplify if required.
分析给定的逻辑图时，应从输入端到输出端，写出每个门输出的表达式，然后组合得到总表达式，必要时进行化简。
5. Boolean Algebra Simplification | 布尔代数化简
identities to reduce circuits. Key laws include: Identity (A+0=A, A·1=A), Complement (A+A'=1, A·A' ·B=A), and Distributive (A·(B+C)=A·B+A·C). These allow simplification, e.g., Q = A·B + A·B' = A·(B+B') = A.
布尔代数利用恒等式来简化电路。关键定律包括：同一律 (A+0=A, A·1=A)，互补律 (A+A'=1, A·A'=0)，幂等律 (A+A=A, A·A=A)，吸收律 (A+A·B=A) 和分配律 (A·(B+C)=A·B+A·C)。这些可以化简表达式，例如 Q = A·B + A·B' = A·(B+B') = A。
Simplify: Q = A + A'B = A + B (using the rule A + A'B = A + B)
化简：Q = A + A'B = A + B（利用规则 A + A'B = A + B）
6. De Morgan's Theorems | 德摩根定理
De Morgan's laws relate AND and OR operations under negation: (A·B)' = A' + B' and (A+B)' = A' · B' and for simplifying expressions with complemented parentheses. For instance, Q = (A·B + C)' can be broken to (A·B)' · C' = (A' + B') · C'.
德摩根定律将补运算下的AND和OR联系起来：(A·B)' = A' + B' 以及 (A+B)' = A' · B'。它们对于门类型转换和化简带有补括号的表达式至关重要。例如，Q = (A·B + C)' 可分解为 (A·B)' · C' = (A' + B') · C'。
To verify, build truth tables for both sides; they will match in all rows.
验证时，可以为两边建立真值表；它们在所有行上都相同。
7. Universal Gates: Implementing Functions with NAND/NOR | 通用门：用NAND/NOR实现任意函数
by an inverter. By connecting inputs together, a single NAND acts as a NOT: NOT A = (A·A)'. An AND is formed by NAND-NOT: A·B = ((A·B)')'. An OR is built using De Morgan: A + B = (A'·B')' which is NAND of inverted inputs.
任何布尔函数都可以仅用NAND门或仅用NOR门实现。NAND门是与门加非门。将输入接在一起，单个NAND可作非门：NOT A = (A·A)'。与门由NAND加非门组成：A·B = ((A·B)')'。或门则利用德摩根：A + B = (A'·B')'，即对取反输入做NAND。
Similarly, a NOR gate can be turned into a NOT (A+A)', an OR (A+B)'', and an AND by NOR of inverted inputs.
类似地，NOR门可变为非门 (A+A)'，或门 (A+B)'' 以及对取反输入作NOR来实现与门。
8. Karnaugh Maps (K-maps) for Simplification | 卡诺图化简
8) and write the product term for each group. For a two-variable map, the expression F = A'B + AB' + AB simplifies to A + B by grouping the two 1s covering A and the two covering B.
卡诺图提供了一种可视化方法来化简最多四个变量的布尔表达式。单元格排列使得相邻格仅一个变量不同。将1按2的幂次（1,2,4,8）分组，并为每组写出乘积项。对于两变量卡诺图，表达式 F = A'B + AB' + AB 通过覆盖A和B的两组1，可化简为 A + B。
K-maps are highly examinable; always check for possibilities to wrap around edges and corners.
卡诺图是常考内容；务必检查边界和角落的环绕可能性。
9. Combinational Circuit Design: Half Adder | 组合逻辑电路设计：半加器
A half adder adds two single binary digits and produces a sum and a carry. The sum S = A ⊕ ne AND gate. It does not account for a carry input, so it forms the basis of a full adder.
半加器将两个一位二进制数相加，输出和与进位。和 S = A ⊕ B (异或)，进位 C = A · B (与)。电路使用一个异或门和一个与门。它没有考虑进位输入，因此构成了全加器的基础。
Truth table: A B | S C; 00->00, 01->10, 10->10, 11->01.
真值表：A B | S C；00→00, 01→10, 10→10, 11→01。
10. Full Adder Design | 全加器设计
carry-in (Cᵢₙ). It produces a sum S and a carry-out Cₒᵤₜ. The Boolean equations are: S = A ⊕ B ⊕ Cᵢₙ; Cₒᵤₜ = A·B + Cᵢₙ·(A ⊕ B). A full adder can be built using two half adders and an OR gate.
全加器将三个位相加：A、B 和进位输入 (Cᵢₙ)，输出和 S 和进位输出 Cₒᵤₜ。布尔方程为：S = A ⊕ B ⊕ Cᵢₙ；Cₒᵤₜ = A·B + Cᵢₙ·(A ⊕ B)。全加器可用两个半加器和一个或门构成。
Implementing multi-bit adders involves cascading full adders, connecting the carry-out of one to the carry-in of the next (ripple carry adder).
多位加法器的实现需要级联全加器，将一个进位输出连接到下一个进位输入（行波进位加法器）。
11. Multiplexers and Demultiplexers | 多路复用器与解复用器
a single output, controlled by select lines. A 2-to-1 MUX output can be expressed as Q = S'·A + S·B, where S is the select input. This circuit uses NOT, AND, and OR gates.
多路复用器 (MUX) 通过选择线控制，从多个输入信号中选择一个送到单一输出。2选1 MUX的输出可表达为 Q = S'·A + S·B，其中 S 为选择输入。电路使用非门、与门和或门。
ut to one of several outputs based on select lines. For a 1-to-2 DEMUX, outputs are Y₀ = S'·D and Y₁ = S·D.
解复用器 (DEMUX) 执行相反操作：根据选择线将单一输入路由到多个输出之一。1路到2路DEMUX的输出为 Y₀ = S'·D 和 Y₁ = S·D。
12. Sequential Logic: SR Latch (Flip-Flop) | 时序逻辑：SR锁存器（触发器）
forbidden (invalid). The same can be implemented with NAND gates using active-low inputs.
与组合电路不同，时序电路具有存储功能。SR锁存器（置位-复位）是一个基本的1位存储元件。使用或非门时，S=1, R=0 置位 (Q=1)；S=0, R=1 复位 (Q=0)；S=R=0 保持原状态；S=R=1 禁止（无效）。也可以用低电平有效的与非门实现。
The latch demonstrates feedback: outputs connect back to inputs, which is the foundation of flip-flops and registers.
锁存器展示了反馈原理：输出接回输入，这是触发器和寄存器的基础。
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